- •INTRODUCTION TO ASICs
- •1.1 Types of ASICs
- •1.2 Design Flow
- •1.3 Case Study
- •1.4 Economics of ASICs
- •1.5 ASIC Cell Libraries
- •1.6 Summary
- •1.7 Problems
- •1.8 Bibliography
- •1.9 References
- •CMOS LOGIC
- •2.12 References
- •2.1 CMOS Transistors
- •2.2 The CMOS Process
- •2.3 CMOS Design Rules
- •2.4 Combinational Logic Cells
- •2.5 Sequential Logic Cells
- •2.6 Datapath Logic Cells
- •2.7 I/O Cells
- •2.8 Cell Compilers
- •2.9 Summary
- •2.10 Problems
- •2.11 Bibliography
- •ASIC LIBRARY DESIGN
- •3.1 Transistors as Resistors
- •3.3 Logical Effort
- •3.4 Library-Cell Design
- •3.5 Library Architecture
- •3.6 Gate-Array Design
- •3.7 Standard-Cell Design
- •3.8 Datapath-Cell Design
- •3.9 Summary
- •3.10 Problems
- •3.11 Bibliography
- •3.12 References
- •PROGRAMMABLE ASICs
- •4.1 The Antifuse
- •4.2 Static RAM
- •4.4 Practical Issues
- •4.5 Specifications
- •4.6 PREP Benchmarks
- •4.7 FPGA Economics
- •4.8 Summary
- •4.9 Problems
- •4.10 Bibliography
- •4.11 References
- •5.1 Actel ACT
- •5.2 Xilinx LCA
- •5.3 Altera FLEX
- •5.4 Altera MAX
- •5.5 Summary
- •5.6 Problems
- •5.7 Bibliography
- •5.8 References
- •6.1 DC Output
- •6.2 AC Output
- •6.3 DC Input
- •6.4 AC Input
- •6.5 Clock Input
- •6.6 Power Input
- •6.7 Xilinx I/O Block
- •6.8 Other I/O Cells
- •6.9 Summary
- •6.10 Problems
- •6.11 Bibliography
- •6.12 References
- •7.1 Actel ACT
- •7.2 Xilinx LCA
- •7.3 Xilinx EPLD
- •7.4 Altera MAX 5000 and 7000
- •7.5 Altera MAX 9000
- •7.6 Altera FLEX
- •7.7 Summary
- •7.8 Problems
- •7.9 Bibliography
- •7.10 References
- •8.1 Design Systems
- •8.2 Logic Synthesis
- •8.3 The Halfgate ASIC
- •8.3.4 Comparison
- •8.4 Summary
- •8.5 Problems
- •8.6 Bibliography
- •8.7 References
- •9.1 Schematic Entry
- •9.3 PLA Tools
- •9.4 EDIF
- •9.5 CFI Design Representation
- •9.6 Summary
- •9.7 Problems
- •9.8 Bibliography
- •9.9 References
- •VHDL
- •10.1 A Counter
- •10.2 A 4-bit Multiplier
- •10.3 Syntax and Semantics of VHDL
- •10.5 Entities and Architectures
- •10.6 Packages and Libraries
- •10.7 Interface Declarations
- •10.8 Type Declarations
- •10.9 Other Declarations
- •10.10 Sequential Statements
- •10.11 Operators
- •10.12 Arithmetic
- •10.13 Concurrent Statements
- •10.14 Execution
- •10.15 Configurations and Specifications
- •10.16 An Engine Controller
- •10.17 Summary
- •10.18 Problems
- •10.19 Bibliography
- •10.20 References
- •IEEE Language Reference Manual project
- •VERILOG HDL
- •11.1 A Counter
- •11.2 Basics of the Verilog Language
- •11.3 Operators
- •11.4 Hierarchy
- •11.5 Procedures and Assignments
- •11.6 Timing Controls and Delay
- •11.7 Tasks and Functions
- •11.8 Control Statements
- •11.9 Logic-Gate Modeling
- •11.10 Modeling Delay
- •11.11 Altering Parameters
- •11.12 A Viterbi Decoder
- •11.13 Other Verilog Features
- •11.14 Summary
- •11.15 Problems
- •11.16 Bibliography
- •11.17 References
- •12.2 A Comparator/MUX
- •12.3 Inside a Logic Synthesizer
- •12.6 VHDL and Logic Synthesis
- •12.8 Memory Synthesis
- •12.9 The Multiplier
- •12.10 The Engine Controller
- •12.13 Summary
- •12.14 Problems
- •12.15 Bibliography
- •12.16 References
- •SIMULATION
- •13.1 Types of Simulation
- •13.3 Logic Systems
- •13.4 How Logic Simulation
- •13.5 Cell Models
- •13.6 Delay Models
- •13.7 Static Timing Analysis
- •13.8 Formal Verification
- •13.9 Switch-Level Simulation
- •13.11 Summary
- •13.12 Problems
- •13.13 Bibliography
- •13.14 References
- •TEST
- •14.1 The Importance of Test
- •14.2 Boundary-Scan Test
- •14.3 Faults
- •14.4 Fault Simulation
- •14.6 Scan Test
- •14.7 Built-in Self-test
- •14.8 A Simple Test Example
- •14.10 Summary
- •14.11 Problems
- •14.12 Bibliography
- •14.13 References
- •15.1 Physical Design
- •15.3 System Partitioning
- •15.4 Estimating ASIC Size
- •15.5 Power Dissipation
- •15.6 FPGA Partitioning
- •15.7 Partitioning Methods
- •15.8 Summary
- •15.9 Problems
- •15.10 Bibliography
- •15.11 References
- •16.1 Floorplanning
- •16.2 Placement
- •16.3 Physical Design Flow
- •16.4 Information Formats
- •16.5 Summary
- •16.6 Problems
- •16.7 Bibliography
- •16.8 References
- •ROUTING
- •17.1 Global Routing
- •17.2 Detailed Routing
- •17.3 Special Routing
- •17.5 Summary
- •17.6 Problems
- •17.7 Bibliography
- •17.8 References
- •A.2 VHDL Syntax
- •A.3 BNF Index
- •A.5 References
- •B.2 Verilog HDL Syntax
- •B.3 BNF Index
- •B.4 Verilog HDL LRM
- •B.5 Bibliography
- •B.6 References
7.7 Summary
The RC product of the parasitic elements of an antifuse and a pass transistor are not too different. However, an SRAM cell is much larger than an antifuse which leads to coarser interconnect architectures for SRAM-based programmable ASICs. The EPROM device lends itself to large wired-logic structures. These differences in programming technology lead to different architectures:
●The antifuse FPGA architectures are dense and regular.
●The SRAM architectures contain nested structures of interconnect resources.
●The complex PLD architectures use long interconnect lines but achieve deterministic routing.
Table 7.4 is a look-up table for Tables 7.5 and 7.6 , which summarize the features of the logic cells used by the various FPGA vendors.
TABLE 7.4 I/O Cell Tables.
Table Programmable ASIC family Table Programmable ASIC family Actel (ACT 1)
Xilinx (XC3000) |
|
|
|
Actel (ACT 2) |
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|
Xilinx (XC4000) |
|
Xilinx (XC8100) |
|
Altera MAX (EPM 5000) |
Lucent ORCA (2C) |
||
Xilinx EPLD (XC7200/7300) |
Altera FLEX (8000/10k) |
||
Table 7.5 |
|
Table 7.6 |
|
Actel (ACT 3) |
|
AMD MACH 5 |
|
QuickLogic (pASIC 1) |
|
Actel 3200DX |
|
Crosspoint (CP20K) |
|
Altera MAX (EPM 9000) |
|
Altera MAX (EPM 7000) |
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Atmel (AT6000) |
|
|
|
Xilinx LCA (XC5200) |
|
|
|
TABLE 7.5 Programmable ASIC interconnect. |
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||
Actel (ACT 1) |
Xilinx (XC3000) Actel (ACT 2) |
Xilinx |
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(XC4000) |
|
|
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Channeled |
|
|
|
|
|
array with |
|
|
|
Channeled array |
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segmented |
Switch box, |
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Switch box, PIPs |
routing, long |
|||
Interconnect with segmented |
PIPs |
||||
(Programmable |
lines: |
||||
between |
routing, long lines: |
(Programmable |
|||
Interconnect |
|
||||
logic cells |
|
36 trks/ch. |
Interconnect |
||
25 trks/ch. (horiz.); |
Points), 3-state |
||||
(tracks = |
(horiz.); 15 |
Points), 3-state |
|||
13 trks/ch. (vert.); |
internal bus, and |
||||
trks) |
trks/ch. |
internal bus, |
|||
|
long lines |
||||
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< 4 antifuses/path |
(vert.); |
and long lines |
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||||
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< 4 |
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|
antifuses/path |
|
|
Interconnect |
Variable |
Variable |
Variable |
Variable |
|
delay |
|
|
|
|
|
Interconnect Poly diffusion |
32-bit SRAM LUT |
Poly diffusion |
32-bit SRAM |
||
inside logic |
antifuse |
antifuse |
LUT |
||
cells |
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||||
|
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|
Altera (MAX 5000) |
Xilinx EPLD |
QuickLogic |
Actel (ACT 3) |
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(pASIC 1) |
||||
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|
Cross-bar PIA |
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Programmable Channeled |
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(Programmable |
UIM (Universal |
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array with |
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Interconnect Interconnect |
Interconnect Matrix) fully |
segmented |
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between |
Architecture) using |
using EPROM |
populated |
routing, long |
|
logic cells |
programmable-AND |
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EPROM |
antifuse |
lines: <4 |
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||||
|
programmable-AND array |
matrix |
antifuses/path |
||
|
array |
|
|
|
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Interconnect Fixed |
Fixed |
Variable |
Variable |
||
delay |
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|
Interconnect |
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|
Metal metal |
Poly diffusion |
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inside logic EPROM |
EPROM |
||||
antifuse |
antifuse |
||||
cells |
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|
|
Crosspoint (CP20K) |
Altera MAX |
Atmel |
Xilinx LCA |
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|
||||
(MAX 7000) |
(AT6000) |
(XC5200) |
||
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||||
|
|
|
Programmable Interconnect highly between
logic cells interconnected matrix
Interconnect Variable delay
Interconnect Metal metal inside logic
cells antifuse
|
Programmable Switch box, |
||
Fixed cross-bar PIA |
regular, local, |
PIPs |
|
(Programmable |
and express |
(Programmable |
|
Interconnect |
|||
Interconnect |
bus scheme |
||
Points), 3-state |
|||
Architecture) |
with line |
||
internal bus, |
|||
|
repeaters |
||
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and long lines |
||
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Fixed |
Variable |
Variable |
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EEPROM |
SRAM |
16-bit SRAM |
|
LUT |
|||
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|
TABLE 7.6 Programmable ASIC interconnect (continued).
|
Xilinx (XC8100) |
|
Channeled array with |
Interconnect |
segmented routing, |
between logic |
long lines. |
cells |
Programmable fully |
|
populated antifuse |
|
matrix. |
Interconnect delay Variable
Interconnect
Antifuse
inside logic cells
AMD MACH 5
Interconnect between logic
EPROM
cells
programmable array
Interconnect delay Fixed
Interconnect
EPROM
inside logic cells
Lucent ORCA 2C
Switch box, SRAM programmable interconnect, 3-state internal bus, and long lines
Variable
SRAM LUTs and
MUXs
Actel 3200DX Channeled gate array
with segmented routing, long lines Variable
Poly diffusion antifuse
Altera FLEX 8000/10k
Row and column FastTrack between LABs
Fixed with small variation in delay in row FastTrack LAB local
interconnect between LEs. 16-bit SRAM LUT in LE.
Altera MAX 9000
Row and column FastTrack between LABs
Fixed Programmable AND array inside LAB, EEPROM MUXes
The key points covered in this chapter are:
●The difference between deterministic and nondeterministic interconnect
●Estimating interconnect delay
●Elmore s constant
Next, in Chapter 8, we shall cover the software you need to design with the various
7.8 Problems
* = Difficult, ** = Very difficult, *** = Extremely difficult
7.1(*Xilinx interconnect, 120 min.)
●a. Write a minitutorial (one or two pages) explaining what you need to know to run and use the XACT delay calculator. Explain how to choose the part, set the display preferences, make connections to CLBs and the interconnect, and obtain timing figures.
●b. Use the XACT editor to determine typical delays using the longlines, a switch matrix, the PIPs, and BIDI buffers (see the Xilinx data book for more detailed explanations of the interconnect structure). Draw six different typical paths using these elements and show the components of delay. Include screen shots showing the layout of the paths and cells with detailed explanations of the figures.
●c. Construct a path using the TBUFs, the three-state buffers, driving a longline (do not forget the pull-up). Show the XACT calculated delay for your path and explain the number from data book parameters (list them and the page number from the data book).
●d. Extend one simple path to the I/O and explain the input and output timing, again using the data book.
●e. Include screen shots from the layout editor showing you example paths.
●f. Bury all the ASCII (but not binary) files you used and the tools produced inside your report using Hidden Text. Include explanations as to what these files are and which parts of the report they go with. This includes any schematic files, netlist files, and all files produced by the Xilinx tools. Use a separate directory for this problem and make a list in your report of all files (binary and ASCII) with explanations of what each file is.
7.2(*Actel interconnect, 120 min.) Use the Actel chip editor to explore the
properties of the interconnect scheme in a similar fashion to Problem 7.1 with
the following changes: in part b make at least six different paths using various antifuse connections and explain the numbers from the delay calculator. Omit part c.
7.3 (*Altera MAX interconnect, 120 min.) Use the Altera tools to determine the properties of the MAX or FLEX interconnect in a similar fashion to Problem 7.1
with the following changes: In parts b and c construct at least six example circuits that show the various paths through the FastTrack or PIA chip-level interconnect,
the local LAB array, the LAB, and the macrocells.
7.4(**Custom ASICs, 120 min.)
●a. Write a minitutorial (one or two pages) explaining how to run an ASIC tool (Compass/Mentor/Cadence/Tanner). Enter a simple circuit (using schematic entry or synthesis and cells from a cell library) and obtain a delay estimate.
●b. Construct at least six example circuits that show various logic paths using various logic cells (for example: an inverter, a full adder).
●c. Perform a timing simulation (either using a static timing verifier or using a logic simulator). Compare your results with those from a data book.
●d. Extract the circuit to include the parasitic capacitances from layout in your circuit netlist and run a simulation to predict the delays.
●e. Compare the results that include routing capacitance with the data book values for the logic cell delays and with the values predicted before routing.
●f. Extend one simple path to the outputs of the chip by including I/O pads in your circuit and explain the input and output timing predictions.
●g. Bury the ASCII files you used and the tools produced inside your report.
7.5(**Actel stubs, 60 min.)
●a. Which metal layers do you think Actel assigns to the horizontal and vertical interconnect in the ACT 1 3 architectures and why?
●b. Why do the ACT 1 3 input stubs not extend over more than two channels above and below the Logic Modules, since this would reduce the need for LVTs?
●c. The ACT 2 data sheet describes the output stubs as twisted (or interwoven) so that they occupy only four tracks. Show that the stubs occupy four vertical tracks whether they are twisted or not.
●d. Suggest the real reason for the twisted stubs.
7.6(A three-input NAND in ACT 1, 30 min.) The macros that require two
ACT 1 modules include the three-input NAND (others include four-input NAND, AND, NOR).
●a. What is the problem with trying to implement a three-input NAND gate using the Actel ACT 1 Logic Module?
●b. Suggest a modification to the ACT 1 Logic Module that would allow the implementation of a three-input NAND using one of your new Logic Modules.
●c. Can you think of a reason why Actel did not use your modification to its Logic Module design? Hi nt: The modification has to do with routing, and not the logic itself.
7.7(*Actel architecture, 60 min.) This is a long but relatively straightforward
problem that reverse-engineers the Actel architecture. If you measured the chip photo on the front of the April 1990 Actel data book, you would find the following:
1.Die height (scribe to scribe) = 170 mm.
2.Channel height = 8 mm (there are 7 full-height and 2 half-height channels).
3.Logic Module height = 5 mm (there are 8 rows of Logic Modules).
4.Column (Logic Module) width = 4.2 mm.
(The scribe line is an area at the edge of a die where a cut is made by a diamond saw when the dice are separated.) An Actel 1010 die in 2 m m technology is 240 mil high by 360 mil wide (p. 4-17 in the 1990 data book). Assuming these data book dimensions are scribe to scribe, calculate (a) the Logic Module height, (b) the channel height, and (c) the column (Logic Module) width.
Given that there are 25 tracks per horizontal channel, and 13 tracks per column in the vertical direction, calculate (d) the horizontal channel track spacing and (e) the vertical channel track spacing. (f) Using the fact that each output stub spans two channels above and below the Logic Module, calculate the height of the output stub.
We can now estimate the capacitance of the Logic Module stubs and interconnect. Assume the interconnect capacitance is 0.2 pFmm 1 . (g) Calculate the capacitance of an output stub and an input stub. (h) Calculate the width and thus the capacitance of the horizontal tracks that are from four columns to 44 columns long.
You should not have to make any other assumptions to calculate these figures, but if you do, state them clearly. The figures you have calculated are summarized in Table 7.2 .
7.8 (Xilinx bank shots, 20 min.) Figure 7.11 shows a magic box. Explain how to use a bank shot to enter one side of the box, bounce off another, and exit on a third side. What is the delay involved in this maneuver?
FIGURE 7.11 A Xilinx magic box showing one set of connections from connection 1 (Problem 7.8).