B.6 References
Page numbers in brackets after a reference indicate its location in the chapter body.
Capilano. 1997. LogicWorks Verilog Modeler: Interactive Circuit Simulation Software for Windows and Macintosh. Menlo Park, CA: Capilano Computing, 102 p. ISBN 0201895854. TK7888.4.L64 (as cataloged by the LOC). Addison-Wesley also gives the following additional ISBN numbers for this work: ISBN 0-201-49885-5 (Windows book and software), ISBN 0-201-49884-7 (Macintosh book and software); also available bundled with LogicWorks 3: ISBN 0-201-87436-9 (Macintosh), ISBN 0-201-87437-7 (Windows).
Golze, U., and P. Blinzer. 1996. VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design. New York: Springer, 358 p. ISBN 3540600329. TK7874.75.G65. Four pages of references. Includes a version of VeriWell from Wellsprings Solutions.
IEEE 1364-1995. IEEE Standard Description Language Based on the Verilog® Hardware Description Language. 688 p. ISBN 1-55937-727-5. IEEE Ref. SH94418-NYF. Published by The IEEE, Inc., 345 East 47th Street, New York, NY 10017, USA. Inside the United States, IEEE standards may be ordered at 1-800-678-4333. See also http://www.ieee.org and http://stdsbbs.ieee.org . This standard was approved by the IEEE on 12 December, 1995; and approved by ANSI on 1 August, 1996 (and thus these two organizations have different publication dates). Contents: overview (4 pages); lexical conventions (8 pages); data types (13 pages); expressions (18 pages); scheduling semantics (5 pages); assignments (4 pages); gate and switch level modeling (31 pages); user-defined primitives (11 pages); behavioral modeling (26 pages); tasks and functions (6 pages); disabling of named blocks and tasks (1 page); hierarchical structures (16 pages); specify blocks (18 pages); system tasks and functions (35 pages); value change dump file (11 pages); compiler directives (8 pages); PLI TF and ACC interface mechanism (6 pages); using ACC routines (36 pages); ACC routine definitions (178 pages); using TF routines (5 pages); TF routine definitions (76 pages); using VPI routines (6 pages); VPI routine definitions (25 pages); formal syntax definition; list of keywords; system tasks and functions; compiler directives; acc_user.h ; veriuser.h ; vpi_user.h . [ reference location ]
Smith, D. J. 1996. HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.
Madison, AL: Doone Publications, 448 p. ISBN 0965193438. TK7874.6.S62.
Sternheim, E., R. Singh, and Y. Trivedi. 1990. Digital Design with Verilog HDL. Cupertino, CA: Automata Publishing, 215 p. ISBN 0962748803. TK7885.7.S74.
Thomas, D. E., and P. Moorby. 1991. The Verilog Hardware Description Language. Boston, MA: Kluwer, 223 p. ISBN 0-7923-9126-8, TK7885.7.T48 (1st ed.). ISBN 0-7923-9523-9 (2nd ed.). ISBN 0792397231 (3rd ed.).
12.12Optimization of the Viterbi Decoder 625
12.13Summary 628
12.14Problems 629
12.15Bibliography 638
12.16References 639
13 SIMULATION 641
13.1Types of Simulation 641
13.2The Comparator/MUX Example 643
13.2.1Structural Simulation 644
13.2.2Static Timing Analysis 647
13.2.3Gate-Level Simulation 648
13.2.4Net Capacitance 650
13.3Logic Systems 652
13.3.1Signal Resolution 653
13.3.2Logic Strength 653
13.4How Logic Simulation Works 656
13.4.1VHDL Simulation Cycle 658
13.4.2Delay 658
13.5Cell Models 659
13.5.1Primitive Models 659
13.5.2Synopsys Models 660
13.5.3Verilog Models 661
13.5.4VHDL Models 663
13.5.5VITAL Models 664
13.5.6SDF in Simulation 667
13.6Delay Models 669
13.6.1Using a Library Data Book 670
13.6.2Input-Slope Delay Model 672
13.6.3Limitations of Logic Simulation 674
13.7Static Timing Analysis 675
13.7.1Hold Time 678
13.7.2Entry Delay 679
13.7.3Exit Delay 680
13.7.4External Setup Time 681
13.8Formal Verification 682
13.8.1An Example 682
13.8.2Understanding Formal Verification 684