Level Two Interface

8.3AXI control signals in the processor

This section describes the processor implementation of the AXI control signals:

For additional information about AXI, see the AMBA AXI Protocol Specification.

The AXI protocol is burst-based. Every transaction has address and control information on the address channel that describes the nature of the data to be transferred. The data is transferred between master and slave using a write channel to the slave or a read channel to the master. In write transactions, where all the data flows from the master to the slave, the AXI has an additional write response channel to enable the slave to signal to the master the completion of the write transaction.

The AXI protocol permits address information to be issued ahead of the actual data transfer and enables support for multiple outstanding transactions in addition to out-of-order completion of transactions.

Figure 8-2 shows how a read transaction uses the read address and read data channels.

Figure 8-2 Channel architecture of reads

Figure 8-3 shows how a write transaction uses the write address, write data, and write response channels.

Write response channel

Write response

Figure 8-3 Channel architecture of writes

Level Two Interface

8.3.1Channel definition

Each of the five independent channels consists of a set of information signals and uses a two-way VALID and READY handshake mechanism.

The information source uses the VALID signal to show when valid data is available on the channel. The destination uses the READY signal to show when it can accept the data. Both the

read data channel and the write data channel also include a LAST signal to indicate when the transfer of the final data item within a transaction takes place.

Read Address channel

The read address channel is used in every transaction and carries all the required read address and control information for that transaction. The AXI supports the following mechanisms:

•variable-length bursts, from 1 to 16 data transfers per burst

•bursts with a transfer size of eight bits up to the maximum data bus width

•wrapping, incrementing, and fixed address bursts

•atomic operations, using exclusive and locked access

•system-level caching and buffering control

•Secure and privileged access.

Write address channel

The write address channel is used in every transaction and carries all the required write address and control information for that transaction. The AXI supports the following mechanisms:

•variable-length bursts, from 1 to 16 data transfers per burst

•bursts with a transfer size of eight bits up to the maximum data bus width

•wrapping, incrementing, and fixed address bursts

•atomic operations, using exclusive and locked access

•system-level caching and buffering control

•Secure and privileged access.

Read data channel

The read data channel conveys both the read data and any read response information from the slave back to the master. The read data channel includes:

•the data bus, that is 32 bits wide for the Peripheral port, and 64 bits wide for the Data Read/Write port, Instruction port and DMA port

•a read response indicating the completion status of the read transaction.

Write data channel

The write data channel conveys the write data from the master to the slave and includes:

•the data bus, that is 32 bits wide for the Peripheral port, and 64 bits wide for the Data Read/Write port, Instruction port and DMA port

•one byte lane strobe for every eight data bits, indicating the bytes of the data bus that are valid.

Write response channel

The write response channel provides a way for the slave to respond to write transactions. All write transactions use completion signaling.

Level Two Interface

Note

The completion signal occurs once for each burst, not for each individual data transfer within the burst.

8.3.2Signal name suffixes

The signal name for each of the interfaces denotes the interface that it applies to. The signals have one of these suffixes:

The second character in the signal name indicates if the data direction is a read, R, or write, W.

For example, AxSIZE[2:0] is called ARSIZEI[2:0] for reads in the Instruction Fetch Interface.

8.3.3Address channel signals

The address channel control signals in the processor are:

•AxLEN[3:0]

•AxSIZE[2:0] on page 8-11

•AxBURST[1:0] on page 8-11

•AxLOCK[1:0] on page 8-11

•AxCACHE[3:0] on page 8-12

•AxPROT[2:0] on page 8-12

•AxSIDEBAND[4:0] on page 8-13.

AxLEN[3:0]

The AxLEN[3:0] signal indicates the number of transfers in a burst. Table 8-2 shows the values of AxLEN that the processor uses.

Table 8-2 AxLEN[3:0] encoding

Level Two Interface

AxSIZE[2:0]

This signal indicates the size of each transfer. Table 8-3 shows the supported transfer sizes.

Table 8-3 AxSIZE[2:0] encoding

AxBURST[1:0]

The AxBURST[1:0] signals indicate a fixed, incrementing or wrapping burst. Table 8-4 shows the burst types that the ARM1176JZ-S processor supports.

The processor uses:

•Wrapping bursts for some cache line fills

•Incrementing bursts for accesses to Noncacheable memory, including instruction fetches.

AxLOCK[1:0]

The AxLOCK[1:0] signal indicates the lock type of access. The processor supports all locked type accesses. The instruction port only generates Normal access types. The DMA port only generates Normal access types. The Data Read/Write port generates all access types, Normal, exclusive and locked access.

Table 8-5 shows the values of AxLOCK that the processor supports.

Table 8-5 AxLOCK[1:0] encoding

Level Two Interface

AxCACHE[3:0]

The AxCACHE[3:0] signals indicate the bufferable, cacheable, write-through, write-back, and

allocate attributes of the transaction. These attributes are for the level two memory system. Table 8-6 shows the correspondence between the AxCACHE[3:0] encoding and TLB

cacheable attributes.

AxPROT[2:0]

The AxPROT[2:0] signal indicates the protection level of the transaction, that is if the transaction is:

•normal or privileged

•Secure or Non-secure

•Data access or Instruction access.

All transactions from the instruction port are marked as instruction accesses, ARPROTI[2] = 1.

Transactions from the DMA port are marked as instruction accesses, AxPROTD[2] = 1, if the transaction is to or from the Instruction TCM, and as data accesses, AxPROTD[2] = 0, for

transfers to or from the Data TCM.

Transactions on the peripheral and data read/write ports are marked as data accesses.

Table 8-7 shows the supported values for AxPROT[2:0].

Table 8-7 AxPROT[2:0] encoding

Level Two Interface

AxSIDEBAND[4:0]

The AxSIDEBAND[4:1] signals indicate the bufferable, cacheable, write-through, write-back, and allocate attributes of the level one memory. AxSIDEBAND[0] indicates the Shared

attribute. Table 8-8 shows the correspondence between the AxSIDEBAND[4:1] encoding and the TLB cacheable attributes for the Read/Write, Peripheral, and DMA ports.

a. The ARM1176JZ-S processor does not support write allocate.

Table 8-9 shows the correspondence between the ARSIDEBANDI[4:1] encoding and the TLB cacheable attributes for the Instruction port.

Table 8-9 ARSIDEBANDI[4:1] encoding

These signals are not part of the AXI protocol and are added for additional information.