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CS 220 / ARM / ARM1176JZ-S Technical Reference Mmanual.pdf
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Summary of ARM1136J-S and ARM1176JZ-S Processor Differences

This new IFAR is updated on prefetch aborts and contains the faulty instruction address.

Note

In Jazelle state, the IFAR is not as accurate as in ARM and Thumb states. In Jazelle state the IFAR does not contain the address of the faulty bytecode but only the address of the word or double-word that includes the faulty bytecode.

B.2.9 Fault Status Register

The fault status registers in the ARM1176JZ-S processor now use bit[12] to determine if the external aborts are SLVERR or DECERR.

B.2.10 Prefetch Unit

In ARM1136J-S processors, the Prefetch Unit has a three stage instruction buffer.

In ARM1176JZ-S processors, the Prefetch Unit has a seven stage instruction buffer. This improves the performance of branch folding.

B.2.11 System control coprocessor operations

The CP15 c15 debug operations and registers are Implementation Defined and there is no roadmap for debuggers to use them. These functionalities add complexity to the logic, require a large validation effort and might introduce some security holes. As a consequence, many CP15 c15 debug operations and registers that are part of the ARM1136J-S processor are removed in ARM1176JZ-S processors. The ARM1176JZ-S processor only retains a small subset of the ARM1136J-S functionality. Direct read/write access to the TLB lockdown entries is present in the two cores but the exact implementation of this feature has been changed.

Table B-2 lists the CP15 c15 registers and operations common to both ARM1176JZ-S and

ARM1136J-S processors.

Table B-2 CP15 c15 features common to ARM1136J-S and ARM1176JZ-S processors

CRn

Opcode_1

CRm

Opcode_2

Register Function

 

 

 

 

 

c15

0

c2

4

Peripheral Memory Remap

 

 

 

 

 

 

 

c12

0

Performance Monitor Control

 

 

 

 

 

 

 

 

1

Cycle Counter

 

 

 

 

 

 

 

 

2

Count Register 0

 

 

 

 

 

 

 

 

3

Count Register 1

 

 

 

 

 

 

3

c8

0

Instruction Cache Master Valid

 

 

 

 

 

 

 

c12

0

Data Cache Master Valid

 

 

 

 

 

 

5a

c4

2

TLB Lockdown Index

 

 

c5

2

TLB Lockdown VA

 

 

 

 

 

 

 

c6

2

TLB Lockdown PA

 

 

 

 

 

 

 

c7

2

TLB Lockdown Attributes

a. Only applies for Lockdown entries.

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Summary of ARM1136J-S and ARM1176JZ-S Processor Differences

Table B-3 lists the features that are implemented in the ARM1136J-S processor but not in

ARM1176JZ-S processors.

Table B-3 CP15 c15 only found in ARM1136J-S processors

CRn

Opcode_1

CRm

Opcode_2

Register Function

 

 

 

 

 

c15

0

c2

0

Data Memory Remap Register

 

 

 

 

 

 

 

 

1

Instruction Memory Remap Register

 

 

 

 

 

 

 

 

2

DMA Memory Remap Register

 

 

 

 

 

 

3

C0

0

Data Debug Cache

 

 

 

 

 

 

 

 

1

Instruction Debug Cache

 

 

 

 

 

 

 

C2

0

Data TAG RAM Read Operation

 

 

 

 

 

 

 

 

1

Instruction TAG RAM Read Operation

 

 

 

 

 

 

 

C4

1

Instruction Cache RAM Data Read Operation

 

 

 

 

 

 

5

C4

0

Data MicroTLB Entry Operation

 

 

 

 

 

 

 

 

1

Instruction MicroTLB Entry Operation

 

 

 

 

 

 

 

 

2

Read Main TLB Entrya

 

 

 

4

Write Main TLB Entrya

 

 

C5

0

Data MicroTLB VA

 

 

 

 

 

 

 

 

1

Instruction MicroTLB VA

 

 

 

 

 

 

 

 

2

Main TLB VAa

 

 

C6

0

Data MicroTLB PA

 

 

 

 

 

 

 

 

1

Instruction MicroTLB PA

 

 

 

 

 

 

 

 

2

Main TLB PAa

 

 

C7

0

Data MicroTLB Attribute

 

 

 

 

 

 

 

 

1

Instruction MicroTLB Attribute

 

 

 

 

 

 

 

 

2

Main TLB Attributea

c15

5

C14

 

Main TLB Valid

 

 

 

 

 

 

7

C0

0

Cache Debug Control

 

 

 

 

 

 

 

 

1

TLB Debug Control

a.In the ARM1136J-S processor is possible to read and write all TLB entries. In ARM1176JZ-S processor you can only read or write the lockdown entries.

B.2.12 DMA

The ARM1176JZ-S processor transfers all data as part of the DMA transfer from TCM to external memory. ARM1136J-S processors only transfer dirty data at a granularity of four words for the Data TCM.

The DMA in the ARM1176JZ-S processor now supports burst accesses in addition to single accesses.

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Summary of ARM1136J-S and ARM1176JZ-S Processor Differences

B.2.13 Debug

Debug changes between ARM1136J-S and ARM1176JZ-S processors include:

TrustZone

Debug test access port

ETM

System metrics.

TrustZone

The ARM1136J-S processor implements the debug v6 architecture but ARM1176JZ-S processors implement the debug v6.1 architecture. Debug v6.1 architecture accounts for TrustZone implementations.

The ARM1176JZ-S processor supports three levels of debug:

debug everywhere

debug in Non-secure and Secure user

debug in Non-secure only.

Additional input signals, SPIDEN and SPNIDEN, configure the level of debug with corresponding bits, SUIDEN and SUNIDEN, in the CP15 Control Register where:

SU stands for Secure User

SP for Secure Privileged

I for Invasive, for example watchpoints and breakpoints

NI for Non-invasive, for example trace and performance monitoring

DEN for Debug Enable.

EDBGRQ

In the ARM1176JZ-S processor Halting debug-mode is entered when EDBGRQ is asserted regardless of the selection of Debug state in DSCR[15:14].

Debug test access port

The ARM1136J-S processor requires external synchronization of the system and test clocks, that is outside processor core.

The ARM1176JZ-S processor performs this synchronization internally.

ETM

The ETM11RV macrocell supports the ARM1136J-S processor whereas the CoreSight

ETM11 macrocell supports both the ARM1136J-S and ARM1176JZ-S processors.

System metrics

In Debug state the system metrics counters are disabled in the ARM1176JZ-S processor.

B.2.14 Level two interface

The external interfaces of the two processors are different to this extent:

The ARM1136J-S processor has four 64-bit AHB-Lite interfaces:

Instruction

Data Read

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Summary of ARM1136J-S and ARM1176JZ-S Processor Differences

Data Write

DMA

It has one 32-bit AHB-Lite Peripheral interface.

The ARM1176JZ-S processor has three 64-bit AXI interfaces:

Instruction

Data Read/Write

DMA

It has one 32-bit AXI Peripheral interface.

B.2.15 Memory BIST

MBISTWE from the ARM1136J-S processor is extended to 8 bits, MBISTWE[7:0], in ARM1176JZ-S processors to enable control of individual write enables for bit and byte write RAMs.

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