Introduction
Table 1-13 summarizes condition codes.
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Table 1-13 Condition codes |
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Suffix |
Description |
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EQ |
Equal |
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NE |
Not equal |
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HS/CS |
Unsigned higher or same, carry set |
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LO/CC |
Unsigned lower, carry clear |
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MI |
Negative, minus |
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PL |
Positive or zero, plus |
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VS |
Overflow |
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VC |
No overflow |
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HI |
Unsigned higher |
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LS |
Unsigned lower or same |
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GE |
Signed greater or equal |
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LT |
Signed less than |
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GT |
Signed greater than |
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LE |
Signed less than or equal |
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AL |
Always |
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1.10.2Thumb instruction set summary
Table 1-14 summarizes the Thumb instruction set.
Table 1-14 Thumb instruction set summary
Operation |
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Assembler |
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Move |
Immediate, update flags |
MOV <Rd>, #<immed_8> |
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LowReg to LowReg, update flags |
MOV <Rd>, <Rm> |
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HighReg to LowReg |
MOV <Rd>, <Rm> |
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LowReg to HighReg |
MOV <Rd>, <Rm> |
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HighReg to HighReg |
MOV <Rd>, <Rm> |
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Copy |
CPY <Rd>, <Rm> |
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Arithmetic |
Add |
ADD <Rd>, <Rn>, #<immed_3> |
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Add immediate |
ADD <Rd>, #<immed_8> |
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Add LowReg and LowReg, update flags |
ADD <Rd>, <Rn>, <Rm> |
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Add HighReg to LowReg |
ADD <Rd>, <Rm> |
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Add LowReg to HighReg |
ADD <Rd>, <Rm> |
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Copyright © 2004-2009 ARM Limited. All rights reserved. |
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Introduction |
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Table 1-14 Thumb instruction set summary (continued) |
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Operation |
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Assembler |
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Add HighReg to HighReg |
ADD <Rd>, <Rm> |
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Add immediate to PC |
ADD <Rd>, PC, #<immed_8*4> |
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Add immediate to SP |
ADD <Rd>, SP, #<immed_8*4> |
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Add immediate to SP |
ADD SP, #<immed_7*4> |
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ADD SP, SP, #<immed_7*4> |
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Add with carry |
ADC <Rd>, <Rs> |
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Subtract immediate |
SUB <Rd>, <Rn>, #<immed_3> |
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Subtract immediate |
SUB <Rd>, #<immed_8> |
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Subtract |
SUB <Rd>, <Rn>, <Rm> |
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Subtract immediate from SP |
SUB SP, #<immed_7*4> |
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Subtract with carry |
SBC <Rd>, <Rm> |
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Negate |
NEG <Rd>, <Rm> |
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Multiply |
MUL <Rd>, <Rm> |
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Compare |
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Compare immediate |
CMP <Rn>, #<immed_8> |
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Compare LowReg and LowReg, update flags |
CMP <Rn>, <Rm> |
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Compare LowReg and HighReg, update flags |
CMP <Rn>, <Rm> |
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Compare HighReg and LowReg, update flags |
CMP <Rn>, <Rm> |
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Compare HighReg and HighReg, update flags |
CMP <Rn>, <Rm> |
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Compare negative |
CMN <Rn>, <Rm> |
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Logical |
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AND |
AND <Rd>, <Rm> |
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XOR |
EOR <Rd>, <Rm> |
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OR |
ORR <Rd>, <Rm> |
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Bit clear |
BIC <Rd>, <Rm> |
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Move NOT |
MVN <Rd>, <Rm> |
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Test bits |
TST <Rd>, <Rm> |
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Shift/Rotate |
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Logical shift left |
LSL <Rd>, <Rm>, #<immed_5> |
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LSL <Rd>, <Rs> |
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Logical shift right |
LSR <Rd>, <Rm>, #<immed_5> |
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LSR <Rd>, <Rs> |
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Arithmetic shift right |
ASR <Rd>, <Rm>, #<immed_5> |
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ASR <Rd>, <Rs> |
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Rotate right |
ROR <Rd>, <Rs> |
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Branch |
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Conditional |
B{cond} <label> |
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Unconditional |
B <label> |
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ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
1-43 |
||
ID012410 |
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Non-Confidential, Unrestricted Access |
|
|
Introduction
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Table 1-14 Thumb instruction set summary (continued) |
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Operation |
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Assembler |
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Branch with link |
BL <label> |
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Branch, link and exchange |
BLX <label> |
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Branch, link and exchange |
BLX <Rm> |
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Branch and exchange |
BX <Rm> |
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Load |
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With immediate offset |
- |
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Word |
LDR <Rd>, [<Rn>, #<immed_5*4>] |
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Halfword |
LDRH <Rd>, [<Rn>, #<immed_5*2>] |
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Byte |
LDRB <Rd>, [<Rn>, #<immed_5>] |
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With register offset |
- |
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Word |
LDR <Rd>, [<Rn>, <Rm>] |
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Halfword |
LDRH <Rd>, [<Rn>, <Rm>] |
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Signed halfword |
LDRSH <Rd>, [<Rn>, <Rm>] |
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Byte |
LDRB <Rd>, [<Rn>, <Rm>] |
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Signed byte |
LDRSB <Rd>, [<Rn>, <Rm>] |
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PC-relative |
LDR <Rd>, [PC, #<immed_8*4>] |
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SP-relative |
LDR <Rd>, [SP, #<immed_8*4>] |
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Multiple |
LDMIA <Rn>!, <reglist> |
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Store |
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With immediate offset |
- |
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Word |
STR <Rd>, [<Rn>, #<immed_5*4>] |
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Halfword |
STRH <Rd>, [<Rn>, #<immed_5*2>] |
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Byte |
STRB <Rd>, [<Rn>, #<immed_5>] |
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With register offset |
- |
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Word |
STR <Rd>, [<Rn>, <Rm>] |
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Halfword |
STRH <Rd>, [<Rn>, <Rm>] |
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Byte |
STRB <Rd>, [<Rn>, <Rm>] |
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SP-relative |
STR <Rd>, [SP, #<immed_8*4>] |
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Multiple |
STMIA <Rn>!, <reglist> |
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Push/Pop |
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Push registers onto stack |
PUSH <reglist> |
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Push LR and registers onto stack |
PUSH <reglist, LR> |
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Pop registers from stack |
POP <reglist> |
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Pop registers and PC from stack |
POP <reglist, PC> |
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Change state |
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Change processor state |
CPS <effect> <iflags> |
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Change endianness |
SETEND <endian_specifier> |
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ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
1-44 |
||
ID012410 |
|
Non-Confidential, Unrestricted Access |
|
|
Introduction
Table 1-14 Thumb instruction set summary (continued)
Operation |
|
Assembler |
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Byte-reverse |
Byte-reverse word |
REV <Rd>, <Rm> |
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Byte-reverse halfword |
REV16 <Rd>, <Rm> |
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Byte-reverse signed halfword |
REVSH <Rd>, <Rm> |
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Supervisor call |
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SVC <immed_8> |
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Software breakpoint |
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BKPT <immed_8> |
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Sign or zero extend |
Sign extend 16 to 32 |
SXTH<Rd>, <Rm> |
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Sign extend 8 to 32 |
SXTB<Rd>, <Rm> |
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Zero extend 16 to 32 |
UXTH<Rd>, <Rm> |
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Zero extend 8 to 32 |
UXTB<Rd>, <Rm> |
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ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
1-45 |
ID012410 |
Non-Confidential, Unrestricted Access |
|