Level Two Interface

8.1About the level two interface

The level two memory interface exists to provide a high-bandwidth interface to second level caches, on-chip RAM, peripherals, and interfaces to external memory.

It is a key feature in ensuring high system performance, providing a higher bandwidth mechanism for filling the caches in a cache miss than has existed on previous ARM processors.

The processor level two interconnect system uses the following 64-bit wide AXI interfaces:

•Instruction Fetch Interface

•Data Read/Write Interface

•DMA Interface.

Another interface is also provided, the Peripheral Interface. This is a 32-bit AXI interface.

Figure 8-1 shows the level two interconnect interfaces.

Figure 8-1 Level two interconnect interfaces

These interfaces provide for several simultaneous outstanding transactions, giving the potential for high performance from level two memory systems that support parallelism, and also for high utilization of pipelined memories such as SDRAM.

•No outstanding accesses are issued on the DMA port. The DMA port can issue bursts of 32-bit or 64-bit data when the address is correctly aligned.

•The data read/write port can issue outstanding accesses. The maximum number of outstanding accesses it can issue is two reads and two writes, to give a total of four outstanding accesses.

•The instruction port can issue outstanding read accesses, up to a maximum of two outstanding read accesses.

•No outstanding accesses are issued by the peripheral port.

Each of the four wide interfaces is an AXI interface, with additional signals to support additional features for the level two memory system for multi-level cache support.

The processor does not drive the following AXI ID signals:

•ARIDI

•ARIDRW

•AWIDRW

•WIDRW

•ARIDP

•AWIDP

•WIDP

•ARIDD

Level Two Interface

•AWIDD

•WIDD.

When you connect the processor in an AXI system, you can choose whatever ID value suits your system. The only requirement is that AWID and WID must have the same value.

8.1.1AXI parameters for the level 2 interconnect interfaces

Table 8-1 shows the AXI parameters for the level 2 interconnect interfaces.

Table 8-1 AXI parameters for the level 2 interconnect interfaces

a.The value of 1 means that interleaving or re-ordering cannot occur.

b.The level 2 interconnect interfaces do not implement any AXI ID signals.

8.1.2Level two instruction-side controller

The level two instruction-side controller contains the level two Instruction Fetch Interface. See

Instruction Fetch Interface.

The level two instruction-side controller handles all instruction-side cache misses including those for Noncacheable locations. It is responsible for the sequencing of cache operations for Instruction Cache linefills, making requests for the individual stores through the Prefetch Unit (PU) to the Instruction Cache. The decoupling involved means that the level two instruction-side controller contains some buffering.

Instruction Fetch Interface

The Instruction Fetch Interface is a read-only interface that services the Instruction Cache on cache misses, including the fetching of instructions for the PU that are held in memory marked as Noncacheable. The interface is optimized for cache linefills rather than individual requests.

8.1.3Level two data-side controller

The level two data-side controller is responsible for the level two:

•Data Read/Write Interface

•Peripheral Interface.

Level Two Interface

The level two data-side controller handles:

•All external access requests from the Load Store Unit, including cache misses, data Write-Through operations, and Noncacheable data.

•SWP instructions and semaphore operations. It schedules all reads and writes on the two interfaces, that are closely related.

The level two data-side controller also handles the Peripheral Interface.

The level two data-side controller contains the Refill and Write-Back engines for the Data Cache. These make requests through the Load Store Unit for the individual cache operations that are required. The decoupling involved means that the level two data-side controller contains some buffering. The write buffer is an integral part of the level two data-side controller.

Data Read/Write Interface

The Data Read/Write Interface performs reads and swap reads. It services the Data Cache on cache misses, and reads noncacheable locations.

The Data Read/Write Interface performs writes and swap writes. It services the writes out of the Write Buffer. Multiple writes can be queued up as part of this interface.

Peripheral Interface

The Peripheral Interface is a bidirectional AXI interface that services peripheral devices. In ARM1176JZ-S processors, the Peripheral Interface is used for peripherals that are private to the processor, such as the Vectored Interrupt Controller or Watchdog Timer. Accesses to regions of memory that are marked as Device and Non-Shared are routed to the Peripheral Interface in preference to the Data Read/Write Interface.

Instruction and DMA accesses are not routed to the Peripheral port.

Unaligned accesses and exclusive accesses are not supported by the peripheral port, because they are not supported in Device memory. The order that accesses are presented on the Peripheral Interface, relative to those on the Data Read/Write Interface is not defined, other than Strongly Ordered accesses. For this reason, the peripheral port is expected to be used to access a bus or memory system that is not accessible through the Data Read/Write port. See c15, Peripheral Port Memory Remap Register on page 3-130 to find out how to remap data accesses to a defined address region to the peripheral port. In some systems, designers might not want to use the Peripheral port to access locations in memory that are marked in the page tables as Non-Shared Device. In these cases, you can use the Remap Registers to remap Non-Shared Device to Shared Device, so causing these accesses to be made using the main system memory ports.

8.1.4DMA

The DMA is responsible for:

•Performing all external memory transactions required by the DMA engine, and for requesting accesses from the Instruction TCM and Data TCM as required.

•Queuing the DMA channels as required. The DMA Interface contains several registers that are CP15 registers dedicated for DMA use, see DMA control on page 3-9 for details.

The DMA contains buffering to enable the decoupling of internal and external requests. This is because of variable latency between internal and external accesses.

Level Two Interface

It uses the Prefetch Unit (PU) and the Load Store Unit (LSU) to schedule its accesses to the TCMs.

DMA Interface

The DMA Interface is a bidirectional interface that services the DMA subsystem for writing and reading the TCMs. Although the DMA Interface is bidirectional, it is able to produce a stream of successive accesses that are in the same direction, followed by either an extra stream in the same direction, or a stream in the opposite direction. Correspondingly the direction turnaround is not significantly optimized.

The size of the transfer is given in the parameters of the transfer in the CP15 registers. The transfers are always aligned with the size of the transfer as indicated by the CP15 registers.