Chapter 1

Introduction

This chapter introduces the ARM1176JZ-S processor and its features. It contains the following sections:

•About the processor on page 1-2

•Extensions to ARMv6 on page 1-3

•TrustZone security extensions on page 1-4

•ARM1176JZ-S architecture with Jazelle technology on page 1-6

•Components of the processor on page 1-8

•Power management on page 1-21

•Configurable options on page 1-23

•Pipeline stages on page 1-24

•Typical pipeline operations on page 1-26

•ARM1176JZ-S instruction set summary on page 1-30

•Product revisions on page 1-46.

Introduction

1.1About the processor

The ARM1176JZ-S processor incorporates an integer core that implements the ARM11 ARM architecture v6. It supports the ARM and Thumb™ instruction sets, Jazelle technology to enable direct execution of Java bytecodes, and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.

The ARM1176JZ-S processor features:

•TrustZone™ security extensions

•provision for Intelligent Energy Management (IEM™)

•high-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced Extensible Interface (AXI) level two interfaces supporting prioritized multiprocessor implementations.

•an integer core with integral EmbeddedICE-RT logic

•an eight-stage pipeline

•branch prediction with return stack

•low interrupt latency configuration

•internal coprocessors CP14 and CP15

•external coprocessor interface

•Instruction and Data Memory Management Units (MMUs), managed using MicroTLB structures backed by a unified Main TLB

•Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss (HUM)

•virtually indexed and physically addressed caches

•64-bit interface to both caches

•level one Tightly-Coupled Memory (TCM) that you can use as a local RAM with DMA

•external coprocessor support

•trace support

•JTAG-based debug.

Note

The only functional difference between the ARM1176JZ-S and ARM1176JZF-S processor is that the ARM1176JZF-S processor includes a Vector Floating-Point (VFP) coprocessor.

Introduction

1.2Extensions to ARMv6

The ARM1176JZ-S processor provides support for extensions to ARMv6 that include:

•Store and Load Exclusive instructions for bytes, halfwords and doublewords and a new Clear Exclusive instruction.

•A true no-operation instruction and yield instruction.

•Architectural remap registers.

•Cache size restriction through CP15 c1. You can restrict cache size to 16KB for Operating Systems (OSs) that do not support page coloring.

•Revised use of TEX remap bits. The ARMv6 MMU page table descriptors use a large number of bits to describe all of the options for inner and outer cachability. In reality, it is believed that no application requires all of these options simultaneously. Therefore, it is possible to configure the ARM1176JZ-S processor to support only a small number of options by means of the TEX remap mechanism. This implies a level of indirection in the page table mappings.

The TEX CB encoding table provides two OS managed page table bits. For binary compatibility with existing ARMv6 ports of OSs, this gives a separate mode of operation of the MMU. This is called the TEX remap configuration and is controlled by bit [28] TR in CP15 Register 1.

•Revised use of AP bits. In the ARM1176JZ-S processor the APX and AP[1:0] encoding b111 is Privileged or User mode read only access. AP[0] indicates an abort type, Access Bit fault, when CP15 c1[29] is 1.

Introduction

1.3TrustZone security extensions

Caution

TrustZone security extensions enable a Secure software environment. The technology does not protect the processor from hardware attacks and the implementor must take appropriate steps to secure the hardware and protect the trusted code.

The ARM1176JZ-S processor supports TrustZone security extensions to provide a secure environment for software. This section summarizes processor elements that TrustZone uses. For details of TrustZone, see the ARM Architecture Reference Manual.

The TrustZone approach to integrated system security depends on an established trusted code base. The trusted code is a relatively small block that runs in the Secure world in the processor and provides the foundation for security throughout the system. This security applies from system boot and enforces a level of trust at each stage of a transaction.

The processor has:

•seven operating modes that can be either Secure or Non-secure

•Secure Monitor mode, that is always Secure.

Except when the processor is in Secure Monitor mode, the NS bit in the Secure Configuration Register determines whether the processor runs code in the Secure or Non-secure worlds. The Secure Configuration Register is in CP15 register c1, see c1, Secure Configuration Register on page 3-52.

Secure Monitor mode is used to switch operation between the Secure and Non-secure worlds.

Secure Monitor mode uses these banked registers:

The processor implements this instruction to enter Secure Monitor mode:

The processor implements these TrustZone related signals:

nDMASIRQ Secure DMA transfer request, see c11, DMA Channel Status Register on page 3-117.

nDMAEXTERRIR

Not maskable error DMA interrupt, see c11, DMA Channel Status Register on page 3-117.

SPIDEN Secure privileged invasive debug enable, see Secure Monitor mode and debug on page 13-4.

SPNIDEN Secure privileged non-invasive debug enable, see Secure Monitor mode and debug on page 13-4.

Note

Do not confuse Secure Monitor mode with the Monitor debug-mode.

Introduction

AXI supports trusted peripherals through these signals:

AxPROT[1]

Protection type signal, see AxPROT[2:0] on page 8-12.

RRESP[1:0]

Read response signal, see AXI interface signals on page A-7.

BRESP[1:0]

Write response signal, see AXI interface signals on page A-7.

ETMIASECCTL[1:0] and ETMCPSECCTL[1:0]

TrustZone information for tracing, see Secure control bus on page 15-4.