System Control Coprocessor

The lockdown region of the TLB contains eight entries. TLB organization on page 6-4 describes the structure of the TLB.

The Invalidate TLB unlocked entries operation does not invalidate TLB entries in the lockdown region.

Invalidate TLB Entry by MVA and Invalidate TLB Entry on ASID Match operations invalidate any TLB entries that correspond to the MVA or ASID given in Rd, if they are in the lockdown region or if they are in the set-associative region of the TLB. See c8, TLB Operations Register on page 3-86 for a description of the TLB invalidate operations.

The victim automatically increments after any page table walk that results in a write puts an entry into the lockdown part of the TLB.

To use the TLB Lockdown Register read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c10

•CRm set to c0

•Opcode_2 set to 0.

For example:

Example 3-2 is a code sequence that locks down an entry to the current victim.

3.2.32c10, Memory region remap registers

The purpose of the memory region remap registers is to remap memory region attributes encoded by the TEX[2:0], C, and B bits in the page tables that the Data side, Instruction side, and DMA use. For details of memory remap, see Memory region attributes on page 6-14.

The memory region remap registers are:

•in CP15 c10

•two 32-bit read/write registers banked for the Secure and Non-secure worlds:

—the Primary Region Remap Register

—the Normal Memory Remap Register.

•accessible in privileged modes only.

System Control Coprocessor

These registers apply to all memory accesses and this includes accesses from the Data side, Instruction side, and DMA. Table 3-99 lists the purposes of the individual bits in the Primary Region Remap Register. Table 3-101 on page 3-103 lists the purposes of the individual bits in the Normal Memory Remap Register.

Note

The behavior of the memory region remap registers depends on the TEX remap bit, see c1, Control Register on page 3-44.

Figure 3-57 shows the arrangement of the bits in the Primary Region Remap Register.

Figure 3-57 Primary Region Remap Register format

Table 3-99 lists the functional bits of the Primary Region Remap Register.

Table 3-99 Primary Region Remap Register bit functions

System Control Coprocessor

Table 3-99 Primary Region Remap Register bit functions (continued)

a.The reset values ensure that no remapping occurs at reset

b.Shareable attributes can map for both shared and non-shared memory. If the Shared bit read from the TLB or page tables is 0, then the bit remaps to the Not Shared attributes in this register. If the Shared bit read from the TLB or page tables is 1, then the bit remaps to the Shared attributes of this register.

Table 3-100 lists the encoding of the remapping for the primary memory type.

Table 3-100 Encoding for the remapping of the primary memory type

Figure 3-58 shows the arrangement of the bits in the Normal Memory Remap Register.

Figure 3-58 Normal Memory Remap Register format

Table 3-101 lists how the bit values correspond with the Normal Memory Remap Register functions.

Table 3-101 Normal Memory Remap Register bit functions

System Control Coprocessor

Table 3-101 Normal Memory Remap Register bit functions (continued)

a. The reset values ensure that no remapping occurs at reset.

Table 3-102 lists the encoding for the Inner or Outer cacheable attribute bit fields I0 to I7 and O0 to O7.

Table 3-102 Remap encoding for Inner or Outer cacheable attributes

Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9.