System Control Coprocessor

Table 3-48 lists the results for combinations of the AW and EA bits.

Table 3-48 Operation of the AW and EA bits

AW EA Function

01 All external aborts trapped to Secure Monitor.

11 All external imprecise data aborts trapped to Secure Monitor but the Non-secure world can hide Secure aborts from the Secure Monitor, avoid use of this function.

For more details on the use of Secure Monitor mode, see The NS bit and Secure Monitor mode on page 2-4.

To use the Secure Configuration Register read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c1

•CRm set to c1

•Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c1, c1, 0 ; Read Secure Configuration Register data

MCR p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data

An attempt to access the Secure Configuration Register from any state other than Secure privileged results in an Undefined exception.

3.2.11c1, Secure Debug Enable Register

The purpose of the Secure Debug Enable Register is to provide control of permissions for debug in Secure User mode, see Chapter 13 Debug.

Table 3-49 on page 3-55 lists the purposes of the individual bits in the Secure Debug Enable

Register.

The Secure Debug Enable Register is:

•in CP15 c1

•a 32 bit register in the Secure world only

•accessible in Secure privileged modes only.

Figure 3-30 shows the arrangement of bits in the register.

SBZ

SUNIDEN

SUIDEN

Figure 3-30 Secure Debug Enable Register format

System Control Coprocessor

Table 3-49 lists how the bit values correspond with the Secure Debug Enable Register functions.

Table 3-50 lists the results of attempted access for each mode.

Table 3-50 Results of access to the Coprocessor Access Control Register

To use the Secure Debug Enable Register read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c1

•CRm set to c1

•Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c1, c1, 1 ; Read Secure Debug Enable Register

MCR p15, 0, <Rd>, c1, c1, 1 ; Write Secure Debug Enable Register

3.2.12c1, Non-Secure Access Control Register

The purpose of the Non-Secure Access Control Register is to define the Non-secure access permission for:

•coprocessors

•cache lockdown registers

•TLB lockdown registers

•internal DMA.

Note

This register has no effect on Non-secure access permissions for the debug control coprocessor, CP14, or the system control coprocessor, CP15.

The Non-Secure Access Control Register is:

•in CP15 c1

•a 32 bit register:

—read/write in the Secure world

—read only in the Non-secure world

System Control Coprocessor

•only accessible in privileged modes.

Figure 3-31 shows the arrangement of bits in the register.

Figure 3-31 Non-Secure Access Control Register format

Table 3-51 lists how the bit values correspond with the Non-Secure Access Control Register functions.

a. n is the coprocessor number from 0 to 13.

To use the Non-Secure Access Control Register read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c1

•CRm set to c1

•Opcode_2 set to 2.

For example:

MRC p15, 0, <Rd>, c1, c1, 2 ; Read Non-Secure Access Control Register data

MCR p15, 0, <Rd>, c1, c1, 2 ; Write Non-Secure Access Control Register data

Table 3-52 lists the results of attempted access for each mode.

Table 3-52 Results of access to the Auxiliary Control Register

3.2.13c2, Translation Table Base Register 0

The purpose of the Translation Table Base Register 0 is to hold the physical address of the first-level translation table.

You use Translation Table Base Register 0 for process-specific addresses, where each process maintains a separate first-level page table. On a context switch you must modify both Translation Table Base Register 0 and the Translation Table Base Control Register, if appropriate.

Table 3-53 on page 3-58 lists the purposes of the individual bits in the Translation Table Base Register 0.

The Translation Table Base Register 0 is:

•in CP15 c2

•a 32 bit read/write register banked for Secure and Non-secure worlds

•accessible in privileged modes only.

Figure 3-32 on page 3-58 shows the bit arrangement for the Translation Table Base Register 0.

System Control Coprocessor

a. For an explanation of N see c2, Translation Table Base Control Register on page 3-61.

Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9.

Table 3-54 lists the results of attempted access for each mode.

Table 3-54 Results of access to the Translation Table Base Register 0

A write to the Translation Table Base Register 0 updates the address of the first level translation table from the value in bits [31:7] of the written value, to account for the maximum value of 7 for N. The number of bits of this address that the processor uses, and therefore, the required alignment of the first level translation table, depends on the value of N, see c2, Translation Table Base Control Register on page 3-61.