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Introduction

1.6Power management

The ARM1176JZ-S processor includes several micro-architectural features to reduce energy consumption:

Accurate branch and return prediction, reducing the number of incorrect instruction fetch and decode operations.

Use of physically tagged caches that reduce the number of cache flushes and refills, to save energy in the system.

The use of MicroTLBs reduces the power consumed in translation and protection look-ups for each memory access.

The caches use sequential access information to reduce the number of accesses to the Tag RAMs and to unmatched data RAMs.

Extensive use of gated clocks and gates to disable inputs to unused functional blocks. Because of this, only the logic actively in use to perform a calculation consumes any dynamic power.

Optionally supports IEM. The ARM1176JZ-S is separated into three different blocks to support three different power domains:

all the RAMS

the core logic that is clocked by CLKIN and FREECLKIN

four optional IEM Register Slices to have an asynchronous interface between the Level 2 ports powered by VCore and clocked by CLKIN, and the AXI system powered by VSoc and clocked by ACLK clocks, one for each port.

The ARM1176JZ-S processor support four levels of power management:

Run mode This mode is the normal mode of operation when the processor can use all its functions.

Standby mode

This mode disables most of the processor clocks of the device, while processor remains powered up. This reduces the power drawn to the static leakage current, plus a tiny clock power overhead required to enable the processor to wake up from the standby state. One of the following events cause a transition from the standby mode to the run mode:

an interrupt, either masked or unmasked

a debug request, regardless of whether debug is enabled

reset.

Shutdown mode

This mode powers down the entire processor. The processor must save all states, including cache and TCM state, externally. The processor is returned to the run state by the assertion of reset. The processor saves the states with interrupts disabled, and finishes with a Data Synchronization Barrier operation. The ARM1176JZ-S processor then communicates with the power controller that it is ready to be powered down.

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Introduction

Dormant mode

This mode powers down the processor and leaves the caches and the TCM powered up and maintaining their state. The valid bits remain visible to software to enable you to implement dormant mode. For full implementation of dormant mode you must:

modify the RAM blocks to include an input clamp

implement separate power domains.

For full implementation of dormant mode see ARM1176JZ-S and ARM1176JZ-S Implementation Guide.

For more details of power management features see Chapter 10 Power Control.

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Introduction

1.7Configurable options

Note

These options are configurable features of your ARM1176JZ-S processor implementation. They are not programmable options of the implemented device.

Table 1-2 lists the ARM1176JZ-S processor configurable options.

 

Table 1-2 Configurable options

 

 

Feature

Range of options

 

 

IEM support

Yes or No

 

 

Cache way size

1KB, 2KB, 4KB, 8KB, or 16KB

 

 

Number of cache ways

4, not configurable

 

 

TCM block size

4KB, 8KB, 16KB, or 32KB

 

 

Number of TCM blocks

0, or auto-configuresa to 1 or 2

a. Number of TCM blocks depends only on the size of the TCM RAM.

In addition, the form of the BIST solution for the RAM blocks in the ARM1176JZ-S design is determined when the processor is implemented. For details, see the ARM11 Memory Built-In Self Test Controller Technical Reference Manual.

Table 1-3 lists the default configuration of ARM1176JZ-S processor.

Table 1-3 ARM1176JZ-S processor default configurations

Feature

Default value

 

 

IEM support

No

 

 

Cache way size

4KB

 

 

Number of cache ways

4

 

 

TCM block size

8KB

 

 

Number of TCM blocks

2

 

 

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Introduction

1.8Pipeline stages

Figure 1-2 shows:

the two Fetch stages

a Decode stage

an Issue stage

the four stages of the ARM1176JZ-S integer execution pipeline.

These eight stages make up the processor pipeline.

 

Fe1

 

 

Fe2

 

 

De

 

Iss

 

 

 

 

Sh

 

 

 

ALU

 

 

Sat

 

 

WBex

 

1st fetch

 

 

 

2nd fetch

 

 

 

Instruction

 

 

 

Reg. read

 

 

 

 

 

Shifter

 

 

 

 

 

 

ALU

 

 

 

 

 

Saturation

 

 

 

 

Writeback

 

 

stage

 

 

 

stage

 

 

 

decode

 

 

 

and issue

 

 

 

 

 

stage

 

 

 

 

 

operation

 

 

 

 

 

 

stage

 

 

 

 

Mul/ALU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAC1

 

 

 

MAC2

 

 

MAC3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1st multiply

 

 

2nd multiply

 

 

 

3rd multiply

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

acc. stage

 

 

acc. stage

 

 

 

 

acc. stage

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADD

 

 

 

DC1

 

 

DC2

 

 

WBls

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

Data

 

 

 

 

 

Data

 

 

 

 

Writeback

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

generation

 

 

 

 

cache 1

 

 

 

 

 

cache 2

 

 

 

 

from LSU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1-2 ARM1176JZ-S pipeline stages

 

 

 

From Figure 1-2, the pipeline operations are:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fe1

First stage of instruction fetch where address is issued to memory and data returns

 

 

 

 

 

 

 

from memory

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Fe2

Second stage of instruction fetch and branch prediction.

 

 

 

 

 

 

 

 

 

 

 

 

 

De

Instruction decode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Iss

Register read and instruction issue.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sh

Shifter stage.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALU

Main integer operation calculation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sat

Pipeline stage to enable saturation of integer results.

 

 

 

 

 

 

 

 

 

 

 

 

 

WBex

Write back of data from the multiply or main execution pipelines.

 

 

 

 

 

 

 

MAC1

First stage of the multiply-accumulate pipeline.

 

 

 

 

 

 

 

 

 

 

 

 

 

MAC2

Second stage of the multiply-accumulate pipeline.

 

 

 

 

 

 

 

 

 

 

 

 

 

MAC3

Third stage of the multiply-accumulate pipeline.

 

 

 

 

 

 

 

 

 

 

 

 

 

ADD

Address generation stage.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DC1

First stage of data cache access.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DC2

Second stage of data cache access.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WBls

Write back of data from the Load Store Unit.

 

 

 

 

 

 

 

 

 

 

By overlapping the various stages of operation, the ARM1176JZ-S processor maximizes the clock rate achievable to execute each instruction. It delivers a throughput approaching one instruction for each cycle.

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Introduction

The Fetch stages can hold up to four instructions, where branch prediction is performed on instructions ahead of execution of earlier instructions.

The Issue and Decode stages can contain any instruction in parallel with a predicted branch.

The Execute, Memory, and Write stages can contain a predicted branch, an ALU or multiply instruction, a load/store multiple instruction, and a coprocessor instruction in parallel execution.

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