ARM1176JZ-S™
Revision: r0p7
Technical Reference Manual
Copyright © 2004-2009 ARM Limited. All rights reserved. ARM DDI 0333H (ID012410)
ARM1176JZ-S
Technical Reference Manual
Copyright © 2004-2009 ARM Limited. All rights reserved.
Release Information
Change history
Date |
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Confidentiality |
Change |
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19 |
July 2004 |
A |
Non-Confidential |
First release. |
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18 |
April 2005 |
B |
Non-Confidential |
Minor corrections and enhancements. |
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29 |
June 2005 |
C |
Non-Confidential |
R0p1 changes - addition of CPUCLAMP. |
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Figure 10-1 updated. |
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Section 10.4.3 updated. Table 23-1 updated. |
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Minor corrections and enhancements. |
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22 |
March 2006 |
D |
Non-Confidential |
First release for r0p2. Minor corrections and enhancements. |
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19 |
July 2006 |
E |
Non-Confidential |
Patch update for r0p4. |
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25 |
April 2007 |
F |
Non-Confidential |
Update for r0p6 release. Minor corrections and enhancements. |
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15 |
February 2008 |
G |
Non-Confidential |
Update for r0p7 release. Minor corrections and enhancements. |
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27 November 2009 |
H |
Non-Confidential |
Update for r0p7 maintenance release. Minor corrections and enhancements. |
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Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Figure 14-1 on page 14-2 reprinted with permission from IEEE Std. 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture by IEEE Std. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.
Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
ii |
ID012410 |
Non-Confidential, Unrestricted Access |
|
Contents
ARM1176JZ-S Technical Reference Manual
Preface
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About this manual ..................................................................................................... |
xix |
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Feedback ................................................................................................................. |
xxiii |
Chapter 1 |
Introduction |
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1.1 |
About the processor ................................................................................................. |
1-2 |
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1.2 |
Extensions to ARMv6 .............................................................................................. |
1-3 |
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1.3 |
TrustZone security extensions ................................................................................. |
1-4 |
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1.4 |
ARM1176JZ-S architecture with Jazelle technology ............................................... |
1-6 |
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1.5 |
Components of the processor .................................................................................. |
1-8 |
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1.6 |
Power management ............................................................................................... |
1-21 |
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1.7 |
Configurable options .............................................................................................. |
1-23 |
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1.8 |
Pipeline stages ...................................................................................................... |
1-24 |
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1.9 |
Typical pipeline operations .................................................................................... |
1-26 |
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1.10 |
ARM1176JZ-S instruction set summary ................................................................ |
1-30 |
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1.11 |
Product revisions ................................................................................................... |
1-46 |
Chapter 2 |
Programmer’s Model |
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2.1 |
About the programmer’s model ............................................................................... |
2-2 |
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2.2 |
Secure world and Non-secure world operation with TrustZone ............................... |
2-3 |
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2.3 |
Processor operating states .................................................................................... |
2-12 |
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2.4 |
Instruction length ................................................................................................... |
2-13 |
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2.5 |
Data types .............................................................................................................. |
2-14 |
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2.6 |
Memory formats ..................................................................................................... |
2-15 |
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2.7 |
Addresses in a processor system .......................................................................... |
2-16 |
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2.8 |
Operating modes ................................................................................................... |
2-17 |
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2.9 |
Registers ................................................................................................................ |
2-18 |
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2.10 |
The program status registers ................................................................................. |
2-24 |
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2.11 |
Additional instructions ............................................................................................ |
2-30 |
ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
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ID012410 |
Non-Confidential, Unrestricted Access |
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Contents |
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2.12 |
Exceptions ............................................................................................................. |
2-36 |
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2.13 |
Software considerations ........................................................................................ |
2-59 |
Chapter 3 |
System Control Coprocessor |
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3.1 |
About the system control coprocessor ..................................................................... |
3-2 |
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3.2 |
System control processor registers ....................................................................... |
3-14 |
Chapter 4 |
Unaligned and Mixed-endian Data Access Support |
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4.1 |
About unaligned and mixed-endian support ......................................................... |
... 4-2 |
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4.2 |
Unaligned access support .................................................................................. |
..... 4-3 |
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4.3 |
Endian support ......................................................................................................... |
4-6 |
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4.4 |
Operation of unaligned accesses .......................................................................... |
4-13 |
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4.5 |
Mixed-endian access support ................................................................................ |
4-17 |
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4.6 |
Instructions to reverse bytes in a general-purpose register ................................... |
4-20 |
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4.7 |
Instructions to change the CPSR E bit .................................................................. |
4-21 |
Chapter 5 |
Program Flow Prediction |
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5.1 |
About program flow prediction ................................................................................. |
5-2 |
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5.2 |
Branch prediction ..................................................................................................... |
5-4 |
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5.3 |
Return stack ............................................................................................................. |
5-7 |
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5.4 |
Memory Barriers ...................................................................................................... |
5-8 |
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5.5 |
ARM1176JZ-S IMB implementation ...................................................................... |
5-10 |
Chapter 6 |
Memory Management Unit |
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6.1 |
About the MMU ........................................................................................................ |
6-2 |
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6.2 |
TLB organization ...................................................................................................... |
6-4 |
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6.3 |
Memory access sequence .................................................................................. |
..... 6-7 |
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6.4 |
Enabling and disabling the MMU ............................................................................. |
6-9 |
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6.5 |
Memory access control .......................................................................................... |
6-11 |
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6.6 |
Memory region attributes ....................................................................................... |
6-14 |
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6.7 |
Memory attributes and types ................................................................................. |
6-20 |
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6.8 |
MMU aborts ........................................................................................................... |
6-27 |
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6.9 |
MMU fault checking ............................................................................................... |
6-29 |
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6.10 |
Fault status and address .................................................................................... |
... 6-34 |
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6.11 |
Hardware page table translation ............................................................................ |
6-36 |
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6.12 |
MMU descriptors .................................................................................................... |
6-43 |
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6.13 |
MMU software-accessible registers ....................................................................... |
6-53 |
Chapter 7 |
Level One Memory System |
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7.1 |
About the level one memory system ..................................................................... |
... 7-2 |
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7.2 |
Cache organization .................................................................................................. |
7-3 |
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7.3 |
Tightly-coupled memory .......................................................................................... |
7-7 |
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7.4 |
DMA ....................................................................................................................... |
7-10 |
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7.5 |
TCM and cache interactions .................................................................................. |
7-12 |
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7.6 |
Write buffer ............................................................................................................ |
7-16 |
Chapter 8 |
Level Two Interface |
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8.1 |
About the level two interface .................................................................................... |
8-2 |
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8.2 |
Synchronization primitives ....................................................................................... |
8-6 |
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8.3 |
AXI control signals in the processor ................................................................... |
..... 8-8 |
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8.4 |
Instruction Fetch Interface transfers ...................................................................... |
8-14 |
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8.5 |
Data Read/Write Interface transfers ...................................................................... |
8-15 |
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8.6 |
Peripheral Interface transfers ................................................................................ |
8-41 |
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8.7 |
Endianness ............................................................................................................ |
8-42 |
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8.8 |
Locked access ....................................................................................................... |
8-43 |
Chapter 9 |
Clocking and Resets |
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9.1 |
About clocking and resets ........................................................................................ |
9-2 |
ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
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ID012410 |
Non-Confidential, Unrestricted Access |
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Contents |
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9.2 |
Clocking and resets with no IEM ............................................................................. |
9-3 |
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9.3 |
Clocking and resets with IEM .................................................................................. |
9-5 |
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9.4 |
Reset modes .......................................................................................................... |
9-10 |
Chapter 10 |
Power Control |
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10.1 |
About power control ............................................................................................... |
10-2 |
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10.2 |
Power management ............................................................................................... |
10-3 |
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10.3 |
Intelligent Energy Management ............................................................................. |
10-6 |
Chapter 11 |
Coprocessor Interface |
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11.1 |
About the coprocessor interface ............................................................................ |
11-2 |
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11.2 |
Coprocessor pipeline ............................................................................................. |
11-3 |
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11.3 |
Token queue management .................................................................................... |
11-9 |
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11.4 |
Token queues ...................................................................................................... |
11-12 |
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11.5 |
Data transfer ........................................................................................................ |
11-15 |
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11.6 |
Operations ........................................................................................................... |
11-19 |
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11.7 |
Multiple coprocessors .......................................................................................... |
11-22 |
Chapter 12 |
Vectored Interrupt Controller Port |
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12.1 |
About the PL192 Vectored Interrupt Controller ...................................................... |
12-2 |
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12.2 |
About the processor VIC port ................................................................................ |
12-3 |
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12.3 |
Timing of the VIC port ............................................................................................ |
12-5 |
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12.4 |
Interrupt entry flowchart ......................................................................................... |
12-7 |
Chapter 13 |
Debug |
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13.1 |
Debug systems ................................................................................................... |
... 13-2 |
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13.2 |
About the debug unit ........................................................................................... |
... 13-3 |
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13.3 |
Debug registers .................................................................................................. |
... 13-5 |
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13.4 |
CP14 registers reset ............................................................................................ |
13-25 |
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13.5 |
CP14 debug instructions ...................................................................................... |
13-26 |
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13.6 |
External debug interface ...................................................................................... |
13-28 |
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13.7 |
Changing the debug enable signals .................................................................... |
13-31 |
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13.8 |
Debug events ....................................................................................................... |
13-32 |
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13.9 |
Debug exception .................................................................................................. |
13-35 |
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13.10 |
Debug state ......................................................................................................... |
13-37 |
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13.11 |
Debug communications channel .......................................................................... |
13-42 |
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13.12 |
Debugging in a cached system ............................................................................ |
13-43 |
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13.13 |
Debugging in a system with TLBs ....................................................................... |
13-44 |
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13.14 |
Monitor debug-mode debugging .......................................................................... |
13-45 |
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13.15 |
Halting debug-mode debugging ........................................................................... |
13-50 |
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13.16 |
External signals ................................................................................................... |
13-52 |
Chapter 14 |
Debug Test Access Port |
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14.1 |
Debug Test Access Port and Debug state .......................................................... |
... 14-2 |
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14.2 |
Synchronizing RealView ICE ................................................................................. |
14-3 |
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14.3 |
Entering Debug state ............................................................................................. |
14-4 |
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14.4 |
Exiting Debug state ................................................................................................ |
14-5 |
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14.5 |
The DBGTAP port and debug registers ................................................................. |
14-6 |
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14.6 |
Debug registers .................................................................................................. |
... 14-8 |
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14.7 |
Using the Debug Test Access Port ...................................................................... |
14-21 |
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14.8 |
Debug sequences ................................................................................................ |
14-29 |
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14.9 |
Programming debug events ................................................................................. |
14-40 |
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14.10 |
Monitor debug-mode debugging .......................................................................... |
14-42 |
Chapter 15 |
Trace Interface Port |
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15.1 |
About the ETM interface ........................................................................................ |
15-2 |
ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
v |
ID012410 |
Non-Confidential, Unrestricted Access |
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Contents |
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Chapter 16 |
Cycle Timings and Interlock Behavior |
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16.1 |
About cycle timings and interlock behavior ............................................................ |
16-2 |
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16.2 |
Register interlock examples ................................................................................... |
16-6 |
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16.3 |
Data processing instructions .................................................................................. |
16-7 |
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16.4 |
QADD, QDADD, QSUB, and QDSUB instructions ................................................ |
16-9 |
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16.5 |
ARMv6 media data-processing ............................................................................ |
16-10 |
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16.6 |
ARMv6 Sum of Absolute Differences (SAD) ........................................................ |
16-11 |
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16.7 |
Multiplies .............................................................................................................. |
16-12 |
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16.8 |
Branches .............................................................................................................. |
16-14 |
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16.9 |
Processor state updating instructions .................................................................. |
16-15 |
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16.10 |
Single load and store instructions ........................................................................ |
16-16 |
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16.11 |
Load and Store Double instructions ..................................................................... |
16-19 |
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16.12 |
Load and Store Multiple Instructions ................................................................... |
16-21 |
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16.13 |
RFE and SRS instructions ................................................................................... |
16-23 |
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16.14 |
Synchronization instructions ................................................................................ |
16-24 |
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16.15 |
Coprocessor instructions ..................................................................................... |
16-25 |
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16.16 |
SVC, SMC, BKPT, Undefined, and Prefetch Aborted instructions ...................... |
16-26 |
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16.17 |
No operation ........................................................................................................ |
16-27 |
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16.18 |
Thumb instructions .............................................................................................. |
16-28 |
Chapter 17 |
AC Characteristics |
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17.1 |
Processor timing diagrams .................................................................................... |
17-2 |
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17.2 |
Processor timing parameters ................................................................................. |
17-3 |
Appendix A |
Signal Descriptions |
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A.1 |
Global signals .......................................................................................................... |
A-2 |
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A.2 |
Static configuration signals ...................................................................................... |
A-4 |
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A.3 |
TrustZone internal signals ....................................................................................... |
A-5 |
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A.4 |
Interrupt signals, including VIC interface ................................................................. |
A-6 |
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A.5 |
AXI interface signals ................................................................................................ |
A-7 |
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A.6 |
Coprocessor interface signals ............................................................................... |
A-12 |
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A.7 |
Debug interface signals, including JTAG ............................................................... |
A-14 |
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A.8 |
ETM interface signals ............................................................................................ |
A-15 |
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A.9 |
Test signals ............................................................................................................ |
A-16 |
Appendix B |
Summary of ARM1136J-S and ARM1176JZ-S Processor Differences |
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B.1 |
About the differences between the ARM1136J-S and ARM1176JZ-S processors |
.. B-2 |
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B.2 |
Summary of differences ........................................................................................... |
B-3 |
Appendix C |
Revisions |
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Glossary
ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
vi |
ID012410 |
Non-Confidential, Unrestricted Access |
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