System Control Coprocessor

A read from the Translation Table Base Register 0 returns the complete address of the first level translation table in bits [31:7] of the read value, regardless of the value of N.

To use the Translation Table Base Register 0 read or write CP15 c2 with:

•Opcode_1 set to 0

•CRn set to c2

•CRm set to c0

•Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c2, c0, 0 ; Read Translation Table Base Register 0

MCR p15, 0, <Rd>, c2, c0, 0 ; Write Translation Table Base Register 0

Note

The ARM1176JZ-S processor cannot page table walk from level one cache. Therefore, if C is set to 1, to ensure coherency, you must either store page tables in Inner write-through memory or, if in Inner write-back, you must clean the appropriate cache entries after modification so that the mechanism for the hardware page table walks sees them.

3.2.14c2, Translation Table Base Register 1

The purpose of the Translation Table Base Register 1 is to hold the physical address of the first-level table. The expected use of the Translation Table Base Register 1 is for OS and I/O addresses.

Table 3-55 on page 3-60 lists the purposes of the individual bits in the Translation Table Base Register 1.

The Translation Table Base Register 1 is:

•in CP15 c2

•a 32 bit read/write register banked for Secure and Non-secure worlds

•accessible in privileged modes only.

Figure 3-33 shows the bit arrangement for the Translation Table Base Register 1.

Figure 3-33 Translation Table Base Register 1 format

System Control Coprocessor

Table 3-55 lists how the bit values correspond with the Translation Table Base Register 1 functions.

Table 3-56 lists the results of attempted access for each mode.

Table 3-56 Results of access to the Translation Table Base Register 1

A write to the Translation Table Base Register 1 updates the address of the first level translation table from the value in bits [31:14] of the written value. Bits [13:5] Should Be Zero. The Translation Table Base Register 1 must reside on a 16KB page boundary.

To use the Translation Table Base Register 1 read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c2

•CRm set to c0

•Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c2, c0, 1 ; Read Translation Table Base Register 1

MCR p15, 0, <Rd>, c2, c0, 1 ; Write Translation Table Base Register 1

System Control Coprocessor

Note

The ARM1176JZ-S processor cannot page table walk from level one cache. Therefore, if C is set to 1, to ensure coherency, you must either store page tables in Inner write-through memory or, if in Inner write-back, you must clean the appropriate cache entries after modification so that the mechanism for the hardware page table walks sees them.

3.2.15c2, Translation Table Base Control Register

The purpose of the Translation Table Base Control Register is to determine if a page table miss for a specific VA uses, for its page table walk, either:

•Translation Table Base Register 0. The recommended use is for task-specific addresses

•Translation Table Base Register 1. The recommended use is for operating system and I/O addresses.

Table 3-57 lists the purposes of the individual bits in the Translation Table Base Control

Register.

The Translation Table Base Control Register is:

•in CP15 c2

•a 32 bit read/write register banked for Secure and Non-secure worlds

•accessible in privileged modes only.

Figure 3-34 shows the bit arrangement for the Translation Table Base Register 1.

Figure 3-34 Translation Table Base Control Register format

Table 3-57 lists how the bit values correspond with the Translation Table Base Register 0 functions.

Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9.

Table 3-58 lists the results of attempted access for each mode.

Table 3-58 Results of access to the Translation Table Base Control Register

To use the Translation Table Base Control Register read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c2

•CRm set to c0

•Opcode_2 set to 2.

For example:

MRC p15, 0, <Rd>, c2, c0, 2 ; Read Translation Table Base Control Register MCR p15, 0, <Rd>, c2, c0, 2 ; Write Translation Table Base Control Register

A translation table base register is selected like this:

•If N is set to 0, always use Translation Table Base Register 0. This is the default case at reset. It is backwards compatible with ARMv5 and earlier processors.

•If N is set greater than 0, and bits [31:32-N] of the VA are all 0, use Translation Table Base Register 0, otherwise use Translation Table Base Register 1. N must be in the range 0-7.