Programmer’s Model

2.11Additional instructions

To support extensions to ARMv6, the ARM1176JZ-S processor includes these instructions in addition to those in the ARMv6 and TrustZone architectures:

•Load Register Exclusive instructions, see LDREXB, LDREXH on page 2-31, and LDREXD on page 2-33

•Store Register Exclusive instructions, see STREXB, STREXH on page 2-32, and STREXH on page 2-32

•Clear Register Exclusive instruction, see CLREX on page 2-34

•Yield instruction, see NOP-compatible hints on page 2-34.

2.11.1Load or Store Byte Exclusive

These instruction operate on unsigned data of size byte.

No alignment restrictions apply to the addresses of these instructions.

The LDREXB and STREXB instructions share the same data monitors as the LDREX and STREX instructions, a local and a global monitor for each processor, for shared memory support.

LDREXB

Figure 2-11 shows the format of the Load Register Byte Exclusive, LDREXB, instruction.

Figure 2-11 LDREXB instruction

Syntax

LDREXB{<cond>} <Rxf>, [<Rbase>]

Operation

if ConditionPassed(cond) then processor_id = ExecutingProcessor() Rd = Memory[Rn,1]

if Shared(Rn) ==1 then physical_address=TLB(Rn)

MarkExclusiveGlobal(physical_address,processor_id,1) MarkExclusiveLocal(processor_id)

STREXB

Figure 2-12 shows the format of the Store Register Byte Exclusive, STREXB, instruction.

Programmer’s Model

Operation

if ConditionPassed(cond) then processor_id = ExecutingProcessor() if IsExclusiveLocal(processor_id) then

if Shared(Rn)==1 then physical_address=TLB(Rn)

if IsExclusiveGlobal(physical_address,processor_id,1) then Memory[Rn,1] = Rm

Rd = 0 ClearByAddress(physical_address,1)

Rd = 1

ClearExclusiveLocal(processor_id)

2.11.2 Load or Store Halfword Exclusive

These instructions operate on naturally aligned, unsigned data of size halfword:

•The address in memory must be 16-bit aligned, address[0] == b0

When (A,U) == (0,1), (1,0) or (1,1) in CP15 register 1, the instruction generates alignment faults if this condition is not met.

For more information, see Operation of unaligned accesses on page 4-13.

•The transaction must be a single access or indivisible burst on bus widths < 16 bits

For AXI based systems, the exclusive access signal, AxPROT[4], must remain asserted throughout the burst where AxSIZE < 0x1.

The LDREXH and STREXH instructions share the same data monitors as the LDREX and STREX instructions, a local and a global monitor for each processor, for shared memory support.

LDREXH

Figure 2-13 shows the format of the Load Register Halfword Exclusive, LDREXH, instruction.

Figure 2-13 LDREXH instruction

Syntax

LDREXH{<cond>} <Rd>, [<Rn>]

Operation

if ConditionPassed(cond) then processor_id = ExecutingProcessor() Rd = Memory[Rn,2]

if Shared(Rn) ==1 then physical_address=TLB(Rn)

MarkExclusiveGlobal(physical_address,processor_id,2) MarkExclusiveLocal(processor_id)

Programmer’s Model

LDREXD

Figure 2-15 shows the format of the Load Register Doubleword Exclusive, LDREXD, instruction.

Figure 2-15 LDREXD instruction

Syntax

LDREXD{<cond>} <Rd>, [<Rn>]

Operation

if ConditionPassed(cond) then processor_id = ExecutingProcessor() Rd = Memory[Rn,4]

R(d+1) = Memory[Rn+4,4] if Shared(Rn) ==1 then

physical_address=TLB(Rn) MarkExclusiveGlobal(physical_address,processor_id,8)

MarkExclusiveLocal(processor_id)

STREXD

Figure 2-16 shows the format of the Store Register Doubleword Exclusive, STREXD, instruction.

Figure 2-16 STREXD instruction

Syntax

STREXD{<cond>} <Rd>, <Rm>, [<Rn>]

Operation

if ConditionPassed(cond) then processor_id = ExecutingProcessor() if IsExclusiveLocal(processor_id) then

if Shared(Rn)==1 then physical_address=TLB(Rn)

if IsExclusiveGlobal(physical_address,processor_id,8) then Memory[Rn,4] = Rm

Memory[Rn+4,4] = R(m+1) Rd = 0

ClearByAddress(physical_address,8)

else

Rd =1

else

Memory[Rn,4] = Rm Memory[Rn+4,4] = R(m+1) Rd = 0

else

Rd = 1