Clocking and Resets

9.3Clocking and resets with IEM

This section describes clocking and resets for the processor with IEM:

•Processor clocking with IEM

•Reset with IEM on page 9-8.

9.3.1Processor clocking with IEM

Externally to the processor, you must connect CLKIN and FREECLKIN together.

It is possible to configure each of the four level two ports to instantiate an IEM register slice so that the processor can have up to five clock domains, CLKIN, ACLKI, ACLKRW, ACLKP and ACLKD. Because of the signals SYNCMODEREQI, SYNCMODEREQRW, SYNCMODEREQP, SYNCMODEREQD, SYNCMODEACKI, SYNCMODEACKRW,

SYNCMODEACKP, and SYNCMODEACKD, it is possible to configure each IEM register slice to operate synchronously or asynchronously.

The four level two interfaces and the VCore part of the IEM register slices use dedicated clock enables, ACLKENI, ACLKENRW, ACLKENP, and ACLKEND.

If you configure an IEM register slice to operate asynchronously, its corresponding ACLKEN* signal must be high. For example, when SYNCMODEACKI is low to indicate asynchronous operation of the instruction port slice, the ACLKENI signal must be held high accordingly.

All clocks can be stopped indefinitely without loss of state.

Figure 9-3 on page 9-6 shows the clocks for the processor with IEM.

Clocking and Resets

Figure 9-3 Processor clocks with IEM

Synchronization with IEM

When the core runs at maximum performance, the two clocks for the IEM Register Slice are synchronous. At this point, when frequency and voltage changes have taken effect, the IEM Register Slice can be bypassed. This removes all the latency that the synchronizers introduce. The synchronization interface is a simple request and acknowledge system. Figure 9-4 shows the processor synchronization with such a system.

Clock

SYNCMODEREQ

SYNCMODEACK

Figure 9-4 Processor synchronization with IEM

Clocking and Resets

When maximum performance is required, SYNCMODEREQ is asserted. When the IEM register slice receives this signal it closes its FIFOs to new data, subject to the constraints required by the AXI protocol, waits for the FIFOs to drain, and then switches the multiplexers

so that the AXI master and slave connect directly. The IEM register slice asserts SYNCMODEACK to acknowledge the direct connection.

For reduced performance levels SYNCMODEREQ is deasserted, and the IEM register slice switches the multiplexers and deasserts SYNCMODEACK when it has done so. The protocol

for these signals means that it is possible to connect different IEM register slices together. You can connect SYNCMODEREQ to all the IEM register slices in parallel and AND together the

SYNCMODEACK outputs.

This means that the SYNCMODEACK signal only goes high when all the IEM register slices have asserted their SYNCMODEACK signals. When coming out of bypass mode, all the IEM registers slices take the same number of cycles, so the SYNCMODEACK signals all deassert

at the same time. Alternatively, if necessary, you can daisy chain the IEM register slices together, so that each slice in the chain only closes its inputs when the previous slice has been multiplexed out.

Read latency penalty for synchronous operation with IEM

When the IEM register slices are instantiated, but are synchronous because SYNCMODEREQ is asserted, the read latency is the same as if the IEM register slices were not present. See Read latency penalty with no IEM on page 9-3 and Figure 9-2 on page 9-4.

Read latency penalty for asynchronous operation with IEM

When the IEM register slices are instantiated and in asynchronous mode, data read or write operations incur additional latency because of the synchronization required for the address and the data between the core and the AXI system. The exact latency depends on:

•the clock ratios

•the clock alignments

•the latency of the AXI system.

On average, with zero-wait-state AXI the system incurs a penalty of 2.5 additional CLKIN cycles and 4.5 additional ACLK cycles.

Figure 9-5 on page 9-8 shows the latency that the IEM register slices add in a system with ACLK and CLKIN of the same frequency, but not synchronous. This example AXI system is

zero-wait-state.

Clocking and Resets

Figure 9-5 Read latency with IEM

The latency, from the pipeline cycles associated with cache reading DC1 and DC2 or Fe1 and

Fe2 to the level two AXI interfaces, is the same as that in Figure 9-2 on page 9-4. The level two AXI interface, on the Core side of the IEM register slice, asserts ARVALIDRW or ARVALIDI

in cycle AVC. The IEM register slice must then synchronize the address to the ACLK clock domain on the SoC side. The address is written into an address FIFO in cycle WPA. There are

then two synchronization cycles in the ACLK clock domain, SA1 and SA2, and a buffer cycle before ARVALID is asserted on the SoC side of the IEM register slice in cycle AVS. Read data

returned from the AXI system in cycle RDS passes through the IEM register slice in a similar way. In the ACLK clock domain, the data is written into a data FIFO in cycle WPD. The data then synchronizes in the CLKIN clock domain, in cycles SD1 and SD2, and passes through a buffer cycle before finally passing to the level two interfaces in cycle RDC. When the level two interfaces of the core receive the data, they then pass it back to the LSU or PU in two cycles, see Figure 9-2 on page 9-4.

Each of the IEM register slices, except the peripheral port slice, can store multiple items of read and write data. This means that a burst of data can typically synchronize in fewer cycles than the same number of individual data items. The number of cycles required to synchronize a burst of data depends on:

•the length of the burst

•the ratio of the clock frequencies

•the clock that has the higher frequency

•the latency of the AXI system

•if the operation is a read or write.

9.3.2Reset with IEM

The processor has the following reset inputs:

Clocking and Resets

nVFPRESETIN The nVFPRESETIN signal is not connected and you must tie it LOW.

ARESETIn, ARESETRWn, ARESETPn, ARESETDn

Reset signals for the SoC part of the IEM register slices. All of these are active LOW signals that reset logic in the processor.