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CS 220 / ARM / ARM1176JZ-S Technical Reference Mmanual.pdf

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Introduction

1.9Typical pipeline operations

Figure 1-3 shows all the operations in each of the pipeline stages in the ALU pipeline, the load/store pipeline, and the HUM buffers.

Ex1

Ex2

Ex3

ALU

Sat

Shifter

Calculate

Saturation

ALU

Fe1

Fe2

Iss

operation

writeback

WBex

pipeline

value

Base

1st fetch

2nd fetch

Instruction

read and

MAC1

MAC2

MAC3

stage

decode

instruction

writeback

issue

1st

2nd

3rd

Multiply

multiply

pipeline

Common decode pipeline

stage

ADD

DC1

DC2

WBls

First stage

Second

Data

Load/store

of data

stage of

Writeback

address

cache

data cache

from LSU

pipeline

calculation

access

Hit under

Load miss

waits

miss

Figure 1-3 Typical operations in pipeline stages

Figure 1-4 shows a typical ALU data processing instruction. The processor does not use the load/store pipeline or the HUM buffer.

Fe1

Fe2

Iss

1st fetch

2nd fetch

Instruction

read and

stage

decode

instruction

issue

Common decode pipeline

Ex1	Ex2	Ex3
Sh	ALU	Sat
Shifter	Calculate	Saturation		ALU
operation	writeback	Saturation	WBex	pipeline
operation	value		WBex	pipeline
			Base
MAC1	MAC2	MAC3	register
MAC1	MAC2	MAC3	writeback
			writeback
Not used	Not used	Not used		Multiply
Not used	Not used	Not used		pipeline
				pipeline
ADD	DC1	DC2	WBls

Load/store

Not used

pipeline

Not used

Hit under miss

Figure 1-4 Typical ALU operation

Figure 1-5 on page 1-27 shows a typical multiply operation. The MUL instruction can loop in the MAC1 stage until it has passed through the first part of the multiplier array enough times. The MUL instruction progresses to MAC2 and MAC3 where it passes through the second half of the array once to produce the final result.

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Introduction

				Ex1
				Sh
Fe1	Fe2	De	Iss	Not used
Fe1	Fe2	De	Iss
			Register
1st fetch	2nd fetch	Instruction	read and	MAC1
stage	stage	decode	instruction	MAC1
			issue	1st
				1st
				multiply
	Common decode pipeline			stage
	Common decode pipeline
				ADD
				Not used

Ex2

Ex3

ALU

Sat

Not used

WBex

ALU

pipeline

Base

MAC2

MAC3

writeback

2nd

3rd

Multiply

multiply

pipeline

stage

DC1

DC2

WBls

Load/store

Not used

pipeline

Not used

Hit under miss

Figure 1-5 Typical multiply operation

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Introduction

1.9.1Instruction progression

Figure 1-6 shows an LDR/STR operation that hits in the data cache.

Fe1

Fe2

Iss

1st fetch

2nd fetch

Instruction

read and

stage

decode

instruction

issue

Common decode pipeline

Ex1	Ex2	Ex3
Sh	ALU	Sat
Shifter	Calculate	Saturation		ALU
operation	writeback	Saturation	WBex	pipeline
operation	value		WBex	pipeline
			Base
MAC1	MAC2	MAC3	register
MAC1	MAC2	MAC3	writeback
			writeback
Not used	Not used	Not used		Multiply
Not used	Not used	Not used		pipeline
				pipeline

ADD

DC1

DC2

WBls

Data

First stage

Second

Load/store

of data

stage of

Writeback

address

cache

data cache

from LSU

pipeline

calculation

access

Not used

Hit under miss

Figure 1-6 Progression of an LDR/STR operation

Figure 1-7 shows the progression of an LDM/STM operation that completes by use of the load/store pipeline. Other instructions can use the ALU pipeline at the same time as the LDM/STM completes in the load/store pipeline.

Fe1

Fe2

Iss

1st fetch

2nd fetch

Instruction

read and

stage

decode

instruction

issue

Common decode pipeline

Ex1	Ex2	Ex3
Sh	ALU	Sat
Shifter	Calculate	Saturation		ALU
operation	writeback	Saturation	WBex	pipeline
operation	value		WBex	pipeline
			Base
MAC1	MAC2	MAC3	register
MAC1	MAC2	MAC3	writeback
			writeback
Not used	Not used	Not used		Multiply
Not used	Not used	Not used		pipeline
				pipeline

ADD

DC1

DC2

WBls

Data

First stage

Second

Load/store

of data

stage of

Writeback

address

cache

data cache

from LSU

pipeline

calculation

access

Not used

Hit under

unless a

miss

occurs

Figure 1-7 Progression of an LDM/STM operation

Figure 1-8 on page 1-29 shows the progression of an LDR that misses. When the LDR is in the HUM buffers, other instructions, including independent loads that hit in the cache, can run under it.

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Introduction

Fe1 1

Fe2 2

De 3

Iss 4

1st fetch

2nd fetch

Instruction

read and

stage

decode

instruction

issue

Common decode pipeline

Ex1		Ex2		Ex3
Sh	5	ALU	6	Sat	7
Shifter		Calculate		Saturation			ALU
operation		writeback		Saturation		WBex 8	pipeline
operation		value				WBex 8	pipeline
						Base
MAC1		MAC2		MAC3		register
MAC1		MAC2		MAC3		writeback
						writeback
Not used		Not used		Not used			Multiply
Not used		Not used		Not used			pipeline
							pipeline

ADD 5

DC1 6

DC2 11

WBls 12

First stage

Second

Data

Load/store

of data

stage of

Writeback

address

cache

data cache

from LSU

pipeline

calculation

access

9,10

Hit under

Load

miss

Figure 1-8 Progression of an LDR that misses

See Chapter 16 Cycle Timings and Interlock Behavior for details of instruction cycle timings.

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Introduction

1.10ARM1176JZ-S instruction set summary

This section provides:

•an Extended ARM instruction set summary on page 1-31

•a Thumb instruction set summary on page 1-42.

Table 1-4 lists a key to the ARM and Thumb instruction set tables.

The ARM1176JZ-S processor implements the ARM architecture v6 with ARM Jazelle technology. For a description of the ARM and Thumb instruction sets, see the ARM Architecture Reference Manual. Contact ARM Limited for complete descriptions of all instruction sets.

	Table 1-4 Key to instruction set tables

Symbol	Description

{!}	Update base register after operation if ! present.

{^}	For all STMs and LDMs that do not load the PC, stores or restores the User
	mode banked registers instead of the current mode registers if ^ present, and
	sets the S bit. For LDMs that load the PC, indicates that the CPSR is loaded
	from the SPSR.

B	Byte operation.

H	Halfword operation.

T	Forces execution to be handled as having User mode privilege. Cannot be
	used with pre-indexed addresses.

x	Selects HIGH or LOW 16 bits of register Rm. T selects the HIGH 16 bits,
	T = top, and B selects the LOW 16 bits, B = bottom.

y	Selects HIGH or LOW 16 bits of register Rs. T selects the HIGH 16 bits,
	T = top, and B selects the LOW 16 bits, B = bottom.

{cond}	Updates condition flags if cond present. See Table 1-13 on page 1-42.

{field}	See Table 1-12 on page 1-41.

{S}	Sets condition codes, optional.

<a_mode2>	See Table 1-6 on page 1-38.

<a_mode2P>	See Table 1-7 on page 1-39.

<a_mode3>	See Table 1-8 on page 1-40.

<a_mode4>	See Table 1-9 on page 1-40.

<a_mode5>	See Table 1-10 on page 1-41.

<cp_num>	One of the coprocessors p0 to p15.

<effect>	Specifies the effect required on the interrupt disable bits, A, I, and F in the
	CPSR:
	IE = Interrupt enable
	ID = Interrupt disable.
	<iflags> specifies the bits affected if <effect> is specified.

<endian_specifier>	BE = Set E bit in instruction, set CPSR E bit.
	LE = Reset E bit in instruction, clear CPSR E bit.

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