System Control Coprocessor

Table 3-103 lists the results of attempted access for each mode.

Table 3-103 Results of access to the memory region remap registers

To use the memory region remap registers read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c10

•CRm set to c2

•Opcode_2 set to:

—0, Primary Region Remap Register

—1, Normal Memory Remap Register.

For example:

MRC p15, 0, <Rd>, c10, c2, 0 ;Read Primary Region Remap Register

MCR p15, 0, <Rd>, c10, c2, 0 ;Write Primary Region Remap Register

MRC p15, 0, <Rd>, c10, c2, 1 ;Read Normal Memory Remap Register

MCR p15, 0, <Rd>, c10, c2, 1 ;Write Normal Memory Remap Register

Memory remap occurs in two stages:

1.The processor uses the Primary Region Remap Register to remap the primary memory type, Normal, Device, or Strongly Ordered, and the shareable attribute.

2.For memory regions that the Primary Region Remap Register defines as Normal memory, the processor uses the Normal Memory Remap Register to remap the inner and outer cacheable attributes.

The behavior of the memory region remap registers depends on the TEX remap bit, see c1, Control Register on page 3-44. If the TEX remap bit is set, the entries in the memory region remap registers remap each possible value of the TEX[0], C and B bits in the page tables. You can therefore set your own definitions for these values. If the TEX remap bit is clear, the memory region remap registers are not used and no memory remapping takes place. For more information see Memory region attributes on page 6-14.

The memory region remap registers are expected to remain static during normal operation. When you write to the memory region remap registers, you must invalidate the TLB and perform an IMB operation before you can rely on the new written values. You must also stop the DMA if it is running or queued.

Note

You cannot remap the NS bit. This is for security reasons.

3.2.33c11, DMA identification and status registers

The purpose of the DMA identification and status registers is to define:

•the DMA channels that are physically implemented on the particular device

•the current status of the DMA channels.

System Control Coprocessor

Processes that handle DMA can read this register to determine the physical resources implemented and their availability.

The DMA Identification and Status Register is:

•in CP15 c11

•four 32-bit read-only registers common to Secure and Non-secure worlds

•accessible only in privileged modes.

Figure 3-59 shows the format of DMA identification and status registers 0-3.

C C UNP H H 1 0

Figure 3-59 DMA identification and status registers format

Table 3-104 lists how the bit values correspond with the DMA identification and status registers.

Table 3-104 DMA identification and status register bit functions

a.See Table 3-105 for the function of the channel that Opcode_2 of the MRC instruction determines.

Table 3-105 lists the Opcode_2 values used to select the DMA channel function.

Table 3-105 DMA Identification and Status Register functions

Opcode_2 Function

0Indicates channel present:

0= the channel is not Present

1= the channel is Present.

1Indicates channel queued:

0= the channel is not Queued

1= the channel is Queued.

2Indicates channel running:

0= the channel is not Running

1= the channel is Running.

3Indicates channel interrupting:

0= the channel is not Interrupting

1= the channel is Interrupting, through completion or an error.

System Control Coprocessor

Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control Register on page 3-55. The processor can only access these registers in Privileged modes. Table 3-106 lists the results of attempted access for each mode.

Table 3-106 Results of access to the DMA identification and status registers

To access the DMA identification and status registers in a privileged mode read CP15 with:

•Opcode_1 set to 0

•CRn set to c11

•CRm set to c0

•Opcode_2 set to:

—0, Present

—1, Queued

—2, Running

—3, Interrupting.

For example:

3.2.34c11, DMA User Accessibility Register

The purpose of the DMA User Accessibility Register is to determine if a User mode process can access the registers for each channel.

The DMA User Accessibility Register is:

•in CP15 c11

•a 32-bit read/write register common to the Secure and Non-secure worlds

•accessible in privileged modes only.

Figure 3-60 shows the bit arrangement for the DMA User Accessibility Register.

SBZ/UNP

U U 1 0

Figure 3-60 DMA User Accessibility Register format

System Control Coprocessor

Table 3-107 lists how the bit values correspond with the DMA User Accessibility Register.

Table 3-107 DMA User Accessibility Register bit functions

Field

Bits Function

name

[1]U1 Indicates if a User mode process can access the registers for channel 1:

0 = User mode cannot access channel 1. User mode accesses cause an Undefined exception. This is the reset value.

1 = User mode can access channel 1.

[0]U0 Indicates if a User mode process can access the registers for channel 0:

0 = User mode cannot access channel 0. User mode accesses cause an Undefined exception. This is the reset value.

1 = User mode can access channel 0.

Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control Register on page 3-55. The processor can only access this register in Privileged modes. Table 3-108 lists the results of attempted access for each mode.

Table 3-108 Results of access to the DMA User Accessibility Register

To access the DMA User Accessibility Register read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c11

•CRm set to c1

•Opcode_2 set to0.

For example:

MRC p15, 0, <Rd>, c11, c1, 0 ; Read DMA User Accessibility Register

MCR p15, 0, <Rd>, c11, c1, 0 ; Write DMA User Accessibility Register

The registers that you can access in User mode when the U bit = 1 for the current channel are:

•c11, DMA enable registers on page 3-110

•c11, DMA Control Register on page 3-111

•c11, DMA Internal Start Address Register on page 3-114

•c11, DMA External Start Address Register on page 3-115

•c11, DMA Internal End Address Register on page 3-116

•c11, DMA Channel Status Register on page 3-117.

You can access the DMA channel Number Register, see c11, DMA Channel Number Register on page 3-109, in User mode when the U bit for any channel is 1.

The contents of these registers must be preserved on a task switch if the registers are User-accessible.