A.6 Coprocessor interface signals

Table A-10 lists the interface signals from the core to the coprocessor.

		Table A-10 Core to coprocessor signals

Name	Direction	Description

ACPCANCEL	Output	Asserted to indicate that the instruction is to be canceled.

ACPCANCELT [3:0]	Output	The tag accompanying the cancel signal in ACPCANCEL.

ACPCANCELV	Output	Asserted to indicate that ACPCANCEL is valid.

ACPENABLE[11:0]	Output	Enables the coprocessor when this is asserted. All lines driven by the
		coprocessor must be held to zero when the coprocessor is not enabled.

ACPFINISHV	Output	The finish token from the core WBls stage to the coprocessor Ex6 stage.

ACPFLUSH	Output	Flush broadcast from the core.

ACPFLUSHT[3:0]	Output	The tag to be flushed from.

ACPINSTR [31:0]	Output	The instruction passed from the core Fe2 stage to the coprocessor Decode stage.

ACPINSTRT [3:0]	Output	The tag accompanying the instruction in ACPINSTR.

ACPINSTRV	Output	Asserted to indicate that ACPINSTR carries a valid instruction.

ACPLDDATA [63:0]	Output	The load data from the core to the coprocessor.

ACPLDVALID	Output	Asserted to indicate that the data in ACPLDATA is valid.

ACPPRIV	Output	Asserted to indicate that the core is in Privileged mode.

ACPSTSTOP	Output	Asserted by the core to tell the coprocessor to stop sending store data.

Table A-11 lists the interface signals from the coprocessor to the core.

If no coprocessor is connected, the following control signals must be driven LOW:

•CPALENGHTHHOLD

•CPAACCEPT

•CPAACCEPTHOLD.

		Table A-11 Coprocessor to core signals

Name	Direction	Description

CPAACCEPT	Input	The bounce signal from the coprocessor issue stage to the core Ex2 stage.

CPAACCEPTHOLD	Input	Asserted to indicate that the bounce information in CPAACCEPT is not valid.

CPAACCEPTT [3:0]	Input	The tag accompanying the bounce signal in CPAACCEPT.

CPALENGTH [3:0]	Input	The length information from the coprocessor Decode stage to the core Ex1
		stage.

CPALENGTHHOLD	Input	Asserted to indicate that the length information in CPALENGTH is not valid.

CPALENGTHT [3:0]	Input	The tag accompanying the length signal in CPALENGTH.

CPAPRESENT[11:0]	Input	Indicates the coprocessors that are present.

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Signal Descriptions

		Table A-11 Coprocessor to core signals (continued)

Name	Direction	Description

CPASTDATA [63:0]	Input	The store data passing from the coprocessor to the core.

CPASTDATAT [3:0]	Input	The tag accompanying the store data in CPASTDATA.

CPASTDATAV	Input	Indicates that the store data to the core is valid.

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Signal Descriptions

A.7 Debug interface signals, including JTAG

Table A-12 lists the debug interface signals including JTAG.

		Table A-12 Debug interface signals

Name	Direction	Description

TCK	Input	Debug clock.

RTCK	Output	Returned TCK.

JTAGSYNCBYPASS	Input	Bypass enable of JTAG synchronizers.

DBGTCKEN	Output	Debug clock enable.

DBGnTRST	Input	Debug nTRST.

TDI	Input	JTAG TDI.

TMS	Input	JTAG TMS.

DBGTDI	Output	Synchronized TDI.

DBGTMS	Output	Synchronized TMS.

EDBGRQ	Input	External debug request.

DBGEN	Input	Debug enable.

DBGVERSION[3:0]	Input	JTAG ID Version field. See Device ID code register on page 14-8.

DBGMANID[10:0]	Input	JTAG manufacturer ID field. See Device ID code register on page 14-8.

DBGTDO	Output	Debug TDO.

DBGnTDOEN	Output	Debug nTDOEN.

COMMTX	Output	Comms channel transmit.

COMMRX	Output	Comms channel receive.

DBGACK	Output	Debug acknowledge.

DBGNOPWRDWN	Output	Debugger has requested core is not powered down.

SPIDEN	Input	Secure Privileged Invasive Debug Enable.

SPNIDEN	Input	Secure Privileged Non-Invasive Debug Enable.

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Signal Descriptions

Table A-13 lists the ETM interface signals.

Table A-13 ETM interface signals

Name	Direction	Description

ETMDA[31:3]	Output	ETM data address.

ETMDACTL[17:0]	Output	ETM data control, address phase.

ETMDD[63:0]	Output	ETM data.

ETMDDCTL[3:0]	Output	ETM data control, data phase.

ETMEXTOUT[1:0]	Input	ETM external event to be monitored.

ETMIA[31:0]	Output	ETM instruction address.

ETMIACTL[17:0]	Output	ETM instruction control.

ETMIASECCTL[1:0]	Output	TrustZone trace information.

ETMIARET[31:0]	Output	ETM return instruction address.

ETMPADV[2:0]	Output	ETM pipeline advance.

ETMPWRUP	Input	When HIGH, indicates that the ETM is powered up. When LOW, logic
		supporting the ETM must be clock gated to conserve power.

nETMWFIREADY	Input	When LOW, indicates ETM can accept Wait For Interrupt.

ETMCPADDRESS[14:0]	Output	Coprocessor address.

ETMCPSECCTL[1:0]	Output	Coprocessor Non-secure access and prohibited trace.

ETMCPCOMMIT	Output	Coprocessor commit.

ETMCPENABLE	Output	Coprocessor interface enable.

ETMCPRDATA[31:0]	Input	Coprocessor read data.

ETMCPWDATA[31:0]	Output	Coprocessor write data.

ETMCPWRITE	Output	Coprocessor write control.

EVNTBUS[19:0]	Output	System metrics event bus.

WFIPENDING	Output	Indicates a Pending Wait For Interrupt. Handshakes with
		nETMWFIREADY.

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