List of Tables
ARM1176JZ-S Technical Reference Manual
|
Change history ................................................................................................................................ |
ii |
Table 1-1 |
TCM configurations ................................................................................................................... |
1-13 |
Table 1-2 |
Configurable options ................................................................................................................. |
1-23 |
Table 1-3 |
ARM1176JZ-S processor default configurations ...................................................................... |
1-23 |
Table 1-4 |
Key to instruction set tables ...................................................................................................... |
1-30 |
Table 1-5 |
ARM instruction set summary ................................................................................................... |
1-31 |
Table 1-6 |
Addressing mode 2 ................................................................................................................... |
1-38 |
Table 1-7 |
Addressing mode 2P, post-indexed only .................................................................................. |
1-39 |
Table 1-8 |
Addressing mode 3 ................................................................................................................... |
1-40 |
Table 1-9 |
Addressing mode 4 ................................................................................................................... |
1-40 |
Table 1-10 |
Addressing mode 5 ................................................................................................................... |
1-41 |
Table 1-11 |
Operand2 .................................................................................................................................. |
1-41 |
Table 1-12 |
Fields ........................................................................................................................................ |
1-41 |
Table 1-13 |
Condition codes ........................................................................................................................ |
1-42 |
Table 1-14 |
Thumb instruction set summary ................................................................................................ |
1-42 |
Table 2-1 |
Write access behavior for system control processor registers .................................................... |
2-9 |
Table 2-2 |
Secure Monitor bus signals ....................................................................................................... |
2-11 |
Table 2-3 |
Address types in the processor system .................................................................................... |
2-16 |
Table 2-4 |
Mode structure .......................................................................................................................... |
2-17 |
Table 2-5 |
Register mode identifiers .......................................................................................................... |
2-19 |
Table 2-6 |
GE[3:0] settings ........................................................................................................................ |
2-26 |
Table 2-7 |
PSR mode bit values ................................................................................................................ |
2-28 |
Table 2-8 |
Exception entry and exit ............................................................................................................ |
2-37 |
Table 2-9 |
Exception priorities .................................................................................................................... |
2-57 |
Table 3-1 |
System control coprocessor register functions ........................................................................... |
3-3 |
Table 3-2 |
Summary of CP15 registers and operations ............................................................................. |
3-15 |
Table 3-3 |
Summary of CP15 MCRR operations ....................................................................................... |
3-20 |
Table 3-4 |
Main ID Register bit functions ................................................................................................... |
3-21 |
Table 3-5 |
Results of access to the Main ID Register ................................................................................ |
3-21 |
Table 3-6 |
Cache Type Register bit functions ............................................................................................ |
3-22 |
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Table 3-7 |
Results of access to the Cache Type Register ......................................................................... |
3-23 |
Table 3-8 |
Example Cache Type Register format .................................................................................... |
.. 3-24 |
Table 3-9 |
TCM Status Register bit functions ..................................................................................... |
....... 3-25 |
Table 3-10 |
TLB Type Register bit functions ................................................................................................ |
3-26 |
Table 3-11 |
Results of access to the TLB Type Register ........................................................................... |
.. 3-26 |
Table 3-12 |
Processor Feature Register 0 bit functions ........................................................................... |
.... 3-27 |
Table 3-13 |
Results of access to the Processor Feature Register 0 ............................................................ |
3-27 |
Table 3-14 |
Processor Feature Register 1 bit functions ........................................................................... |
.... 3-28 |
Table 3-15 |
Results of access to the Processor Feature Register 1 ............................................................ |
3-29 |
Table 3-16 |
Debug Feature Register 0 bit functions ............................................................................... |
..... 3-29 |
Table 3-17 |
Results of access to the Debug Feature Register 0 ................................................................. |
3-30 |
Table 3-18 |
Auxiliary Feature Register 0 bit functions ........................................................................... |
...... 3-30 |
Table 3-19 |
Results of access to the Auxiliary Feature Register 0 .............................................................. |
3-31 |
Table 3-20 |
Memory Model Feature Register 0 bit functions ....................................................................... |
3-31 |
Table 3-21 |
Results of access to the Memory Model Feature Register 0 .................................................... |
3-32 |
Table 3-22 |
Memory Model Feature Register 1 bit functions ....................................................................... |
3-33 |
Table 3-23 |
Results of access to the Memory Model Feature Register 1 .................................................... |
3-33 |
Table 3-24 |
Memory Model Feature Register 2 bit functions ....................................................................... |
3-34 |
Table 3-25 |
Results of access to the Memory Model Feature Register 2 .................................................... |
3-35 |
Table 3-26 |
Memory Model Feature Register 3 bit functions ....................................................................... |
3-36 |
Table 3-27 |
Results of access to the Memory Model Feature Register 3 .................................................... |
3-36 |
Table 3-28 |
Instruction Set Attributes Register 0 bit functions .................................................................. |
... 3-37 |
Table 3-29 |
Results of access to the Instruction Set Attributes Register 0 .................................................. |
3-37 |
Table 3-30 |
Instruction Set Attributes Register 1 bit functions .................................................................. |
... 3-38 |
Table 3-31 |
Results of access to the Instruction Set Attributes Register 1 .................................................. |
3-39 |
Table 3-32 |
Instruction Set Attributes Register 2 bit functions .................................................................. |
... 3-39 |
Table 3-33 |
Results of access to the Instruction Set Attributes Register 2 .................................................. |
3-40 |
Table 3-34 |
Instruction Set Attributes Register 3 bit functions .................................................................. |
... 3-41 |
Table 3-35 |
Results of access to the Instruction Set Attributes Register 3 .................................................. |
3-41 |
Table 3-36 |
Instruction Set Attributes Register 4 bit functions .................................................................. |
... 3-42 |
Table 3-37 |
Results of access to the Instruction Set Attributes Register 4 .................................................. |
3-43 |
Table 3-38 |
Results of access to the Instruction Set Attributes Register 5 .................................................. |
3-44 |
Table 3-39 |
Control Register bit functions .................................................................................................... |
3-45 |
Table 3-40 |
Results of access to the Control Register ............................................................................ |
..... 3-47 |
Table 3-41 |
Resultant B bit, U bit, and EE bit values ............................................................................ |
....... 3-48 |
Table 3-42 |
Auxiliary Control Register bit functions ............................................................................. |
........ 3-49 |
Table 3-43 |
Results of access to the Auxiliary Control Register .................................................................. |
3-50 |
Table 3-44 |
Coprocessor Access Control Register bit functions .................................................................. |
3-51 |
Table 3-45 |
Results of access to the Coprocessor Access Control Register ............................................... |
3-52 |
Table 3-46 |
Secure Configuration Register bit functions .......................................................................... |
.... 3-53 |
Table 3-47 |
Operation of the FW and FIQ bits ..................................................................................... |
........ 3-53 |
Table 3-48 |
Operation of the AW and EA bits ...................................................................................... |
........ 3-54 |
Table 3-49 |
Secure Debug Enable Register bit functions ........................................................................... |
. 3-55 |
Table 3-50 |
Results of access to the Coprocessor Access Control Register ............................................... |
3-55 |
Table 3-51 |
Non-Secure Access Control Register bit functions ................................................................... |
3-56 |
Table 3-52 |
Results of access to the Auxiliary Control Register .................................................................. |
3-57 |
Table 3-53 |
Translation Table Base Register 0 bit functions ...................................................................... |
. 3-58 |
Table 3-54 |
Results of access to the Translation Table Base Register 0 .................................................... |
3-58 |
Table 3-55 |
Translation Table Base Register 1 bit functions ...................................................................... |
. 3-60 |
Table 3-56 |
Results of access to the Translation Table Base Register 1 .................................................... |
3-60 |
Table 3-57 |
Translation Table Base Control Register bit functions .............................................................. |
3-61 |
Table 3-58 |
Results of access to the Translation Table Base Control Register ........................................... |
3-62 |
Table 3-59 |
Domain Access Control Register bit functions ......................................................................... |
. 3-63 |
Table 3-60 |
Results of access to the Domain Access Control Register ....................................................... |
3-63 |
Table 3-61 |
Data Fault Status Register bit functions ............................................................................. |
....... 3-64 |
Table 3-62 |
Results of access to the Data Fault Status Register ................................................................. |
3-66 |
Table 3-63 |
Instruction Fault Status Register bit functions ...................................................................... |
..... 3-67 |
Table 3-64 |
Results of access to the Instruction Fault Status Register ........................................................ |
3-67 |
Table 3-65 |
Results of access to the Fault Address Register ...................................................................... |
3-68 |
Table 3-66 |
Results of access to the Instruction Fault Address Register ..................................................... |
3-69 |
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List of Tables |
Table 3-67 |
Functional bits of c7 for Set and Index .............................................................................. |
........ 3-72 |
Table 3-68 |
Cache size and S parameter dependency ................................................................................ |
3-72 |
Table 3-69 |
Functional bits of c7 for MVA .................................................................................................... |
3-73 |
Table 3-70 |
Functional bits of c7 for VA format ............................................................................................ |
3-74 |
Table 3-71 |
Cache operations for entire cache .................................................................................... |
........ 3-74 |
Table 3-72 |
Cache operations for single lines .............................................................................................. |
3-76 |
Table 3-73 |
Cache operations for address ranges .................................................................................. |
..... 3-76 |
Table 3-74 |
Cache Dirty Status Register bit functions ............................................................................ |
..... 3-78 |
Table 3-75 |
Cache operations flush functions ..................................................................................... |
......... 3-79 |
Table 3-76 |
Flush Branch Target Entry using MVA bit functions ................................................................. |
3-80 |
Table 3-77 |
PA Register for successful translation bit functions ................................................................. |
. 3-81 |
Table 3-78 |
PA Register for unsuccessful translation bit functions .............................................................. |
3-82 |
Table 3-79 |
Results of access to the Data Synchronization Barrier operation ............................................. |
3-84 |
Table 3-80 |
Results of access to the Data Memory Barrier operation ......................................................... |
3-85 |
Table 3-81 |
Results of access to the Wait For Interrupt operation ............................................................... |
3-86 |
Table 3-82 |
Results of access to the TLB Operations Register ................................................................... |
3-87 |
Table 3-83 |
Instruction and data cache lockdown register bit functions .................................................... |
... 3-89 |
Table 3-84 |
Results of access to the Instruction and Data Cache Lockdown Register ................................ |
3-89 |
Table 3-85 |
Data TCM Region Register bit functions ............................................................................... |
.... 3-91 |
Table 3-86 |
Results of access to the Data TCM Region Register ................................................................ |
3-91 |
Table 3-87 |
Instruction TCM Region Register bit functions ........................................................................ |
.. 3-92 |
Table 3-88 |
Results of access to the Instruction TCM Region Register ....................................................... |
3-93 |
Table 3-89 |
Data TCM Non-secure Control Access Register bit functions .................................................. |
3-94 |
Table 3-90 |
Effects of NS items for data TCM operation ........................................................................... |
.. 3-95 |
Table 3-91 |
Instruction TCM Non-secure Control Access Register bit functions ......................................... |
3-96 |
Table 3-92 |
Effects of NS items for instruction TCM operation .................................................................... |
3-96 |
Table 3-93 |
TCM Selection Register bit functions ................................................................................. |
....... 3-97 |
Table 3-94 |
Results of access to the TCM Selection Register ..................................................................... |
3-97 |
Table 3-95 |
Cache Behavior Override Register bit functions ....................................................................... |
3-98 |
Table 3-96 |
Results of access to the Cache Behavior Override Register .................................................... |
3-99 |
Table 3-97 |
TLB Lockdown Register bit functions .................................................................................. |
.... 3-100 |
Table 3-98 |
Results of access to the TLB Lockdown Register ................................................................... |
3-100 |
Table 3-99 |
Primary Region Remap Register bit functions ........................................................................ |
3-102 |
Table 3-100 |
Encoding for the remapping of the primary memory type ....................................................... |
3-103 |
Table 3-101 |
Normal Memory Remap Register bit functions ....................................................................... |
3-103 |
Table 3-102 |
Remap encoding for Inner or Outer cacheable attributes ....................................................... |
3-104 |
Table 3-103 |
Results of access to the memory region remap registers ....................................................... |
3-105 |
Table 3-104 |
DMA identification and status register bit functions ................................................................ |
3-106 |
Table 3-105 |
DMA Identification and Status Register functions ................................................................... |
3-106 |
Table 3-106 |
Results of access to the DMA identification and status registers ........................................... |
3-107 |
Table 3-107 |
DMA User Accessibility Register bit functions ....................................................................... |
. 3-108 |
Table 3-108 |
Results of access to the DMA User Accessibility Register ..................................................... |
3-108 |
Table 3-109 |
DMA Channel Number Register bit functions .................................................................. |
....... 3-109 |
Table 3-110 |
Results of access to the DMA Channel Number Register ...................................................... |
3-109 |
Table 3-111 |
Results of access to the DMA enable registers ...................................................................... |
3-111 |
Table 3-112 |
DMA Control Register bit functions .................................................................................. |
....... 3-112 |
Table 3-113 |
Results of access to the DMA Control Register ...................................................................... |
3-113 |
Table 3-114 |
Results of access to the DMA Internal Start Address Register ............................................... |
3-114 |
Table 3-115 |
Results of access to the DMA External Start Address Register ............................................. |
3-115 |
Table 3-116 |
Results of access to the DMA Internal End Address Register ................................................ |
3-116 |
Table 3-117 |
DMA Channel Status Register bit functions ........................................................................... |
. 3-117 |
Table 3-118 |
Results of access to the DMA Channel Status Register ......................................................... |
3-119 |
Table 3-119 |
DMA Context ID Register bit functions ............................................................................... |
.... 3-120 |
Table 3-120 |
Results of access to the DMA Context ID Register ................................................................ |
3-120 |
Table 3-121 |
Secure or Non-secure Vector Base Address Register bit functions ....................................... |
3-121 |
Table 3-122 |
Results of access to the Secure or Non-secure Vector Base Address Register .................... |
3-122 |
Table 3-123 |
Monitor Vector Base Address Register bit functions ............................................................... |
3-123 |
Table 3-124 |
Results of access to the Monitor Vector Base Address Register ............................................ |
3-123 |
Table 3-125 |
Interrupt Status Register bit functions ..................................................................................... |
3-124 |
Table 3-126 |
Results of access to the Interrupt Status Register .................................................................. |
3-124 |
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Table 3-127 |
FCSE PID Register bit functions ............................................................................................. |
3-125 |
Table 3-128 |
Results of access to the FCSE PID Register .......................................................................... |
3-126 |
Table 3-129 |
Context ID Register bit functions ............................................................................................ |
3-128 |
Table 3-130 |
Results of access to the Context ID Register ......................................................................... |
3-128 |
Table 3-131 |
Results of access to the thread and process ID registers ....................................................... |
3-129 |
Table 3-132 |
Peripheral Port Memory Remap Register bit functions ........................................................... |
3-131 |
Table 3-133 |
Results of access to the Peripheral Port Remap Register ...................................................... |
3-131 |
Table 3-134 |
Secure User and Non-secure Access Validation Control Register bit functions ..................... |
3-132 |
Table 3-135 |
Results of access to the Secure User and Non-secure Access Validation Control Register .. |
3-133 |
Table 3-136 |
Performance Monitor Control Register bit functions ............................................................... |
3-134 |
Table 3-137 |
Performance monitoring events .............................................................................................. |
3-135 |
Table 3-138 |
Results of access to the Performance Monitor Control Register ............................................ |
3-137 |
Table 3-139 |
Results of access to the Cycle Counter Register .................................................................... |
3-138 |
Table 3-140 |
Results of access to the Count Register 0 .............................................................................. |
3-139 |
Table 3-141 |
Results of access to the Count Register 1 .............................................................................. |
3-140 |
Table 3-142 |
System validation counter register operations ........................................................................ |
3-140 |
Table 3-143 |
Results of access to the System Validation Counter Register ................................................ |
3-141 |
Table 3-144 |
System Validation Operations Register functions ................................................................... |
3-142 |
Table 3-145 |
Results of access to the System Validation Operations Register ........................................... |
3-143 |
Table 3-146 |
System Validation Cache Size Mask Register bit functions .................................................... |
3-145 |
Table 3-147 |
Results of access to the System Validation Cache Size Mask Register ................................. |
3-146 |
Table 3-148 |
TLB Lockdown Index Register bit functions ............................................................................ |
3-149 |
Table 3-149 |
TLB Lockdown VA Register bit functions ................................................................................ |
3-150 |
Table 3-150 |
TLB Lockdown PA Register bit functions ................................................................................ |
3-150 |
Table 3-151 |
Access permissions APX and AP bit fields encoding ............................................................. |
3-151 |
Table 3-152 |
TLB Lockdown Attributes Register bit functions ..................................................................... |
3-152 |
Table 3-153 |
Results of access to the TLB lockdown access registers ....................................................... |
3-152 |
Table 4-1 |
Unaligned access handling ......................................................................................................... |
4-4 |
Table 4-2 |
Memory access types ............................................................................................................... |
4-13 |
Table 4-3 |
Unalignment fault occurrence when access behavior is architecturally unpredictable ............. |
4-14 |
Table 4-4 |
Legacy endianness using CP15 c1 ........................................................................................... |
4-17 |
Table 4-5 |
Mixed-endian configuration ....................................................................................................... |
4-19 |
Table 4-6 |
B bit, U bit, and EE bit settings ................................................................................................. |
4-19 |
Table 6-1 |
Access permission bit encoding ................................................................................................ |
6-12 |
Table 6-2 |
TEX field, and C and B bit encodings used in page table formats ............................................ |
6-15 |
Table 6-3 |
Cache policy bits ....................................................................................................................... |
6-15 |
Table 6-4 |
Inner and Outer cache policy implementation options .............................................................. |
6-16 |
Table 6-5 |
Effect of remapping memory with TEX remap = 1 .................................................................... |
6-17 |
Table 6-6 |
Values that remap the shareable attribute ................................................................................ |
6-18 |
Table 6-7 |
Primary region type encoding ................................................................................................... |
6-18 |
Table 6-8 |
Inner and outer region remap encoding .................................................................................... |
6-18 |
Table 6-9 |
Memory attributes ..................................................................................................................... |
6-20 |
Table 6-10 |
Memory region backwards compatibility ................................................................................... |
6-26 |
Table 6-11 |
Fault Status Register encoding ................................................................................................. |
6-34 |
Table 6-12 |
Summary of aborts .................................................................................................................... |
6-35 |
Table 6-13 |
Translation table size ................................................................................................................ |
6-43 |
Table 6-14 |
Access types from first-level descriptor bit values .................................................................... |
6-45 |
Table 6-15 |
Access types from second-level descriptor bit values .............................................................. |
6-47 |
Table 6-16 |
CP15 register functions ............................................................................................................. |
6-53 |
Table 6-17 |
CP14 register functions ............................................................................................................. |
6-54 |
Table 7-1 |
TCM configurations ..................................................................................................................... |
7-7 |
Table 7-2 |
Access to Non-secure TCM ........................................................................................................ |
7-8 |
Table 7-3 |
Access to Secure TCM ............................................................................................................... |
7-8 |
Table 7-4 |
Summary of data accesses to TCM and caches ...................................................................... |
7-14 |
Table 7-5 |
Summary of instruction accesses to TCM and caches ............................................................. |
7-15 |
Table 8-1 |
AXI parameters for the level 2 interconnect interfaces ............................................................... |
8-3 |
Table 8-2 |
AxLEN[3:0] encoding ................................................................................................................ |
8-10 |
Table 8-3 |
AxSIZE[2:0] encoding ............................................................................................................... |
8-11 |
Table 8-4 |
AxBURST[1:0] encoding ........................................................................................................... |
8-11 |
Table 8-5 |
AxLOCK[1:0] encoding ............................................................................................................. |
8-11 |
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Table 8-6 |
AxCACHE[3:0] encoding ........................................................................................................... |
8-12 |
Table 8-7 |
AxPROT[2:0] encoding ............................................................................................................. |
8-12 |
Table 8-8 |
AxSIDEBAND[4:1] encoding ..................................................................................................... |
8-13 |
Table 8-9 |
ARSIDEBANDI[4:1] encoding ................................................................................................... |
8-13 |
Table 8-10 |
AXI signals for Cacheable fetches ............................................................................................ |
8-14 |
Table 8-11 |
AXI signals for Noncacheable fetches ...................................................................................... |
8-14 |
Table 8-12 |
Linefill behavior on the AXI interface ........................................................................................ |
8-15 |
Table 8-13 |
Noncacheable LDRB ................................................................................................................ |
8-16 |
Table 8-14 |
Noncacheable LDRH ................................................................................................................ |
8-16 |
Table 8-15 |
Noncacheable LDR or LDM1 .................................................................................................... |
8-17 |
Table 8-16 |
Noncacheable LDRD or LDM2 ................................................................................................. |
8-17 |
Table 8-17 |
Noncacheable LDRD or LDM2 from word 7 ............................................................................. |
8-18 |
Table 8-18 |
Noncacheable LDM3, Strongly Ordered or Device memory ..................................................... |
8-18 |
Table 8-19 |
Noncacheable LDM3, Noncacheable memory or cache disabled ............................................ |
8-18 |
Table 8-20 |
Noncacheable LDM3 from word 6, or 7 .................................................................................... |
8-18 |
Table 8-21 |
Noncacheable LDM4, Strongly Ordered or Device memory ..................................................... |
8-19 |
Table 8-22 |
Noncacheable LDM4, Noncacheable memory or cache disabled ............................................ |
8-19 |
Table 8-23 |
Noncacheable LDM4 from word 5, 6, or 7 ................................................................................ |
8-19 |
Table 8-24 |
Noncacheable LDM5, Strongly Ordered or Device memory ..................................................... |
8-20 |
Table 8-25 |
Noncacheable LDM5, Noncacheable memory or cache disabled ............................................ |
8-20 |
Table 8-26 |
Noncacheable LDM5 from word 4, 5, 6, or 7 ............................................................................ |
8-20 |
Table 8-27 |
Noncacheable LDM6, Strongly Ordered or Device memory ..................................................... |
8-20 |
Table 8-28 |
Noncacheable LDM6, Noncacheable memory or cache disabled ............................................ |
8-21 |
Table 8-29 |
Noncacheable LDM6 from word 3, 4, 5, 6, or 7 ........................................................................ |
8-21 |
Table 8-30 |
Noncacheable LDM7, Strongly Ordered or Device memory ..................................................... |
8-21 |
Table 8-31 |
Noncacheable LDM7, Noncacheable memory or cache disabled ............................................ |
8-21 |
Table 8-32 |
Noncacheable LDM7 from word 2, 3, 4, 5, 6, or 7 .................................................................... |
8-21 |
Table 8-33 |
Noncacheable LDM8 from word 0 ............................................................................................ |
8-22 |
Table 8-34 |
Noncacheable LDM8 from word 1, 2, 3, 4, 5, 6, or 7 ................................................................ |
8-22 |
Table 8-35 |
Noncacheable LDM9 ................................................................................................................ |
8-23 |
Table 8-36 |
Noncacheable LDM10 .............................................................................................................. |
8-23 |
Table 8-37 |
Noncacheable LDM11 .............................................................................................................. |
8-23 |
Table 8-38 |
Noncacheable LDM12 .............................................................................................................. |
8-24 |
Table 8-39 |
Noncacheable LDM13 .............................................................................................................. |
8-24 |
Table 8-40 |
Noncacheable LDM14 .............................................................................................................. |
8-25 |
Table 8-41 |
Noncacheable LDM15 .............................................................................................................. |
8-25 |
Table 8-42 |
Noncacheable LDM16 .............................................................................................................. |
8-25 |
Table 8-43 |
Half-line Write-Back .................................................................................................................. |
8-26 |
Table 8-44 |
Full-line Write-Back ................................................................................................................... |
8-26 |
Table 8-45 |
Cacheable Write-Through or Noncacheable STRB .................................................................. |
8-27 |
Table 8-46 |
Cacheable Write-Through or Noncacheable STRH .................................................................. |
8-27 |
Table 8-47 |
Cacheable Write-Through or Noncacheable STR or STM1 ...................................................... |
8-29 |
Table 8-48 |
Cacheable Write-Through or Noncacheable STRD or STM2 to words 0, 1, 2, 3, 4, 5, or 6 ..... |
8-30 |
Table 8-49 |
Cacheable Write-Through or Noncacheable STM2 to word 7 .................................................. |
8-30 |
Table 8-50 |
Cacheable Write-Through or Noncacheable STM3 to words 0, 1, 2, 3, 4, or 5 ........................ |
8-31 |
Table 8-51 |
Cacheable Write-Through or Noncacheable STM3 to words 6 or 7 ......................................... |
8-31 |
Table 8-52 |
Cacheable Write-Through or Noncacheable STM4 to word 0, 1, 2, 3, or 4 .............................. |
8-32 |
Table 8-53 |
Cacheable Write-Through or Noncacheable STM4 to word 5, 6, or 7 ...................................... |
8-32 |
Table 8-54 |
Cacheable Write-Through or Noncacheable STM5 to word 0, 1, 2, or 3 .................................. |
8-33 |
Table 8-55 |
Cacheable Write-Through or Noncacheable STM5 to word 4, 5, 6, or 7 .................................. |
8-33 |
Table 8-56 |
Cacheable Write-Through or Noncacheable STM6 to word 0, 1, or 2 ...................................... |
8-34 |
Table 8-57 |
Cacheable Write-Through or Noncacheable STM6 to word 3, 4, 5, 6, or 7 .............................. |
8-34 |
Table 8-58 |
Cacheable Write-Through or Noncacheable STM7 to word 0 or 1 ........................................... |
8-35 |
Table 8-59 |
Cacheable Write-Through or Noncacheable STM7 to word 2, 3, 4, 5, 6 or 7 ........................... |
8-35 |
Table 8-60 |
Cacheable Write-Through or Noncacheable STM8 to word 0 .................................................. |
8-36 |
Table 8-61 |
Cacheable Write-Through or Noncacheable STM8 to word 1, 2, 3, 4, 5, 6, or 7 ...................... |
8-36 |
Table 8-62 |
Cacheable Write-Through or Noncacheable STM9 .................................................................. |
8-37 |
Table 8-63 |
Cacheable Write-Through or Noncacheable STM10 ................................................................ |
8-37 |
Table 8-64 |
Cacheable Write-Through or Noncacheable STM11 ................................................................ |
8-38 |
Table 8-65 |
Cacheable Write-Through or Noncacheable STM12 ................................................................ |
8-38 |
ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
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|
|
List of Tables |
Table 8-66 |
Cacheable Write-Through or Noncacheable STM13 ............................................................. |
... 8-39 |
Table 8-67 |
Cacheable Write-Through or Noncacheable STM14 ............................................................. |
... 8-39 |
Table 8-68 |
Cacheable Write-Through or Noncacheable STM15 ............................................................. |
... 8-40 |
Table 8-69 |
Cacheable Write-Through or Noncacheable STM16 ............................................................. |
... 8-40 |
Table 8-70 |
Example Peripheral Interface reads and writes ........................................................................ |
8-41 |
Table 9-1 |
Reset modes ............................................................................................................................. |
9-10 |
Table 11-1 |
Coprocessor instructions .......................................................................................................... |
11-3 |
Table 11-2 |
Coprocessor control signals ...................................................................................................... |
11-4 |
Table 11-3 |
Pipeline stage update ............................................................................................................... |
11-7 |
Table 11-4 |
Addressing of queue buffers ................................................................................................... |
11-10 |
Table 11-5 |
Retirement conditions ............................................................................................................. |
11-20 |
Table 12-1 |
VIC port signals ......................................................................................................................... |
12-3 |
Table 13-1 |
Terms used in register descriptions .................................................................................. |
........ 13-5 |
Table 13-2 |
CP14 debug register map ......................................................................................................... |
13-5 |
Table 13-3 |
Debug ID Register bit field definition ......................................................................................... |
13-7 |
Table 13-4 |
Debug Status and Control Register bit field definitions ............................................................. |
13-8 |
Table 13-5 |
Data Transfer Register bit field definitions ......................................................................... |
..... 13-12 |
Table 13-6 |
Vector Catch Register bit field definitions .......................................................................... |
..... 13-14 |
Table 13-7 |
Summary of debug entry and exception conditions ................................................................ |
13-14 |
Table 13-8 |
Processor breakpoint and watchpoint registers ...................................................................... |
13-16 |
Table 13-9 |
Breakpoint Value Registers, bit field definition ..................................................................... |
... 13-17 |
Table 13-10 |
Processor Breakpoint Control Registers .............................................................................. |
... 13-17 |
Table 13-11 |
Breakpoint Control Registers, bit field definitions ................................................................. |
.. 13-18 |
Table 13-12 |
Meaning of BCR[22:20] bits .................................................................................................... |
13-19 |
Table 13-13 |
Processor Watchpoint Value Registers ................................................................................ |
.. 13-20 |
Table 13-14 |
Watchpoint Value Registers, bit field definitions ................................................................... |
.. 13-21 |
Table 13-15 |
Processor Watchpoint Control Registers .............................................................................. |
.. 13-21 |
Table 13-16 |
Watchpoint Control Registers, bit field definitions ................................................................. |
.. 13-22 |
Table 13-17 |
Debug State Cache Control Register bit functions ................................................................. |
13-24 |
Table 13-18 |
Debug State MMU Control Register bit functions ................................................................... |
13-24 |
Table 13-19 |
CP14 debug instructions ......................................................................................................... |
13-26 |
Table 13-20 |
Debug instruction execution .................................................................................................... |
13-27 |
Table 13-21 |
Secure debug behavior ........................................................................................................... |
13-28 |
Table 13-22 |
Behavior of the processor on debug events ........................................................................... |
13-33 |
Table 13-23 |
Setting of CP15 registers on debug events ........................................................................... |
. 13-34 |
Table 13-24 |
Values in the link register after exceptions ........................................................................ |
..... 13-36 |
Table 13-25 |
Read PC value after Debug state entry ............................................................................... |
... 13-39 |
Table 13-26 |
Example memory operation sequence ................................................................................... |
13-41 |
Table 14-1 |
Supported public instructions .................................................................................................... |
14-6 |
Table 14-2 |
Scan chain 7 register map ...................................................................................................... |
14-19 |
Table 15-1 |
Instruction interface signals ...................................................................................................... |
15-2 |
Table 15-2 |
ETMIACTL[17:0] ....................................................................................................................... |
15-3 |
Table 15-3 |
ETMIASECCTL[1:0] .................................................................................................................. |
15-4 |
Table 15-4 |
Data address interface signals .................................................................................................. |
15-4 |
Table 15-5 |
ETMDACTL[17:0] ...................................................................................................................... |
15-5 |
Table 15-6 |
Data value interface signals ...................................................................................................... |
15-6 |
Table 15-7 |
ETMDDCTL[3:0] ....................................................................................................................... |
15-6 |
Table 15-8 |
ETMPADV[2:0] .......................................................................................................................... |
15-6 |
Table 15-9 |
Coprocessor interface signals ................................................................................................... |
15-7 |
Table 15-10 |
ETMCPSECCTL[1:0] format ............................................................................................. |
........ 15-7 |
Table 15-11 |
Other connections ..................................................................................................................... |
15-8 |
Table 16-1 |
Pipeline stages .......................................................................................................................... |
16-3 |
Table 16-2 |
Definition of cycle timing terms ................................................................................................. |
16-5 |
Table 16-3 |
Register interlock examples ...................................................................................................... |
16-6 |
Table 16-4 |
Data Processing Instruction cycle timing behavior if destination is not PC ............................ |
... 16-7 |
Table 16-5 |
Data Processing Instruction cycle timing behavior if destination is the PC ............................ |
... 16-7 |
Table 16-6 |
QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior ................................... |
16-9 |
Table 16-7 |
ARMv6 media data-processing instructions cycle timing behavior ......................................... |
16-10 |
Table 16-8 |
ARMv6 sum of absolute differences instruction timing behavior ............................................ |
16-11 |
Table 16-9 |
Example interlocks .................................................................................................................. |
16-11 |
ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
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ID012410 |
Non-Confidential, Unrestricted Access |
|
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|
List of Tables |
Table 16-10 |
Example multiply instruction cycle timing behavior ................................................................. |
16-12 |
Table 16-11 |
Branch instruction cycle timing behavior ............................................................................ |
..... 16-14 |
Table 16-12 |
Processor state updating instructions cycle timing behavior .................................................. |
16-15 |
Table 16-13 |
Cycle timing behavior for stores and loads, other than loads to the PC ............................. |
.... 16-16 |
Table 16-14 |
Cycle timing behavior for loads to the PC ........................................................................... |
.... 16-17 |
Table 16-15 |
<addr_md_1cycle> and <addr_md_2cycle> LDR example instruction explanation ............... |
16-17 |
Table 16-16 |
Load and Store Double instructions cycle timing behavior ..................................................... |
16-19 |
Table 16-17 |
<addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction explanation ............. |
16-19 |
Table 16-18 |
Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC ....... |
|
|
16-21 |
|
Table 16-19 |
Cycle timing behavior of Load Multiples, where the PC is in the register list .......................... |
16-22 |
Table 16-20 |
RFE and SRS instructions cycle timing behavior ............................................................. |
....... 16-23 |
Table 16-21 |
Synchronization Instructions cycle timing behavior ................................................................ |
16-24 |
Table 16-22 |
Coprocessor Instructions cycle timing behavior ...................................................................... |
16-25 |
Table 16-23 |
SVC, BKPT, undefined, prefetch aborted instructions cycle timing behavior ......................... |
16-26 |
Table 17-1 |
Global signals ........................................................................................................................... |
17-3 |
Table 17-2 |
AXI signals ................................................................................................................................ |
17-3 |
Table 17-3 |
Coprocessor signals ................................................................................................................. |
17-4 |
Table 17-4 |
ETM interface signals ............................................................................................................... |
17-5 |
Table 17-5 |
Interrupt signals ........................................................................................................................ |
17-5 |
Table 17-6 |
Debug interface signals ............................................................................................................ |
17-5 |
Table 17-7 |
Test signals ............................................................................................................................... |
17-6 |
Table 17-8 |
Static configuration signals ....................................................................................................... |
17-6 |
Table 17-9 |
TrustZone internal signals ......................................................................................................... |
17-6 |
Table A-1 |
Global signals ............................................................................................................................. |
A-2 |
Table A-2 |
Static configuration signals ......................................................................................................... |
A-4 |
Table A-3 |
TrustZone internal signals ........................................................................................................... |
A-5 |
Table A-4 |
Interrupt signals .......................................................................................................................... |
A-6 |
Table A-5 |
Port signal name suffixes ............................................................................................................ |
A-7 |
Table A-6 |
Instruction read port AXI signal implementation ......................................................................... |
A-8 |
Table A-7 |
Data port AXI signal implementation ........................................................................................... |
A-9 |
Table A-8 |
Peripheral port AXI signal implementation ................................................................................ |
A-10 |
Table A-9 |
DMA port signals ....................................................................................................................... |
A-11 |
Table A-10 |
Core to coprocessor signals ..................................................................................................... |
A-12 |
Table A-11 |
Coprocessor to core signals ..................................................................................................... |
A-12 |
Table A-12 |
Debug interface signals ............................................................................................................ |
A-14 |
Table A-13 |
ETM interface signals ............................................................................................................... |
A-15 |
Table A-14 |
Test signals ............................................................................................................................... |
A-16 |
Table B-1 |
TCM for ARM1176JZ-S processors ............................................................................................ |
B-6 |
Table B-2 |
CP15 c15 features common to ARM1136J-S and ARM1176JZ-S processors ........................... |
B-7 |
Table B-3 |
CP15 c15 only found in ARM1136J-S processors ...................................................................... |
B-8 |
Table C-1 |
Differences between issue G and issue H .................................................................................. |
C-1 |
ARM DDI 0333H |
Copyright © 2004-2009 ARM Limited. All rights reserved. |
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