Introduction

1.5Components of the processor

The main components of the ARM1176JZ-S processor are:

•Integer core

•Load Store Unit (LSU) on page 1-11

•Prefetch unit on page 1-11

•Memory system on page 1-12

•AMBA AXI interface on page 1-15

•Coprocessor interface on page 1-17

•Debug on page 1-17

•Instruction cycle summary and interlocks on page 1-19

•System control on page 1-19

•Interrupt handling on page 1-19.

Figure 1-1 shows the structure of the ARM1176JZ-S processor.

System

metrics

Figure 1-1 ARM1176JZ-S processor block diagram

1.5.1Integer core

The ARM1176JZ-S processor is built around the ARM11 integer core. It is an implementation of the ARMv6 architecture and runs the ARM, Thumb, and Java instruction sets. The processor contains EmbeddedICE-RT™ logic and a JTAG debug interface to enable hardware debuggers to communicate with the processor. The following sections describe the core in more detail:

•Instruction set categories on page 1-9

•Conditional execution on page 1-9

•Registers on page 1-9

Introduction

•Modes and exceptions

•Thumb instruction set on page 1-10

•DSP instructions on page 1-10

•Media extensions on page 1-10

•Datapath on page 1-10

•Branch prediction on page 1-11

•Return stack on page 1-11.

Instruction set categories

The main instruction set categories are:

•branch instructions

•data processing instructions

•status register transfer instructions

•load and store instructions

•coprocessor instructions.

•exception-generating instructions.

Note

Only load, store, and swap instructions can access data from memory.

Conditional execution

The processor conditionally executes nearly all ARM instructions. You can decide if the condition code flags, Negative, Zero, Carry, and Overflow, are updated according to their result.

Registers

The ARM1176JZ-S core contains:

•33 general-purpose 32-bit registers

•7 dedicated 32-bit registers.

Note

At any one time, 16 general-purpose registers are visible. The remainder are banked registers used to speed up exception processing.

Modes and exceptions

The core provides a set of operating and exception modes, to support systems combining complex operating systems, user applications, and real-time demands. There are eight operating modes, six of them are exception processing modes:

•User

•Supervisor

•fast interrupt

•normal interrupt

•abort

•system

•Undefined

•Secure Monitor.

Introduction

Thumb instruction set

The Thumb instruction set contains a subset of the most commonly-used 32-bit ARM instructions encoded into 16-bit wide opcodes. This reduces the amount of memory required for instruction storage.

DSP instructions

The DSP extensions to the ARM instruction set provide:

•16-bit data operations

•saturating arithmetic

•MAC operations.

The processor executes multiply instructions using a single-cycle 32x16 implementation. The processor can perform 32x32, 32x16, and 16x16 multiply instructions (MAC).

Media extensions

The ARMv6 instruction set provides media instructions to complement the DSP instructions. There are four media instruction groups:

•Multiplication instructions for handling 16-bit and 32-bit data, including dual-multiplication instructions that operate on both 16-bit halves of their source registers.

This group includes an instruction that improves the performance and size of code for multi-word unsigned multiplications.

•Single Instruction Multiple Data (SIMD) Instructions to perform operations on pairs of 16-bit values held in a single register, or on sets of four 8-bit values held in a single register. The main operations supplied are addition and subtraction, selection, pack, and saturation.

•Instructions to extract bytes and halfwords from registers and zero-extend or sign-extend them. These include a parallel extraction of two bytes followed by extension of each byte to a halfword.

•Unsigned Sum-of-Absolute-Differences (SAD) instructions. This is used in MPEG motion estimation.

Datapath

The datapath consists of three pipelines:

•ALU, shift and Sat pipeline

•MAC pipeline

•load or store pipeline, see Load Store Unit (LSU) on page 1-11.

ALU, shift or Sat pipe

The ALU, shift and Sat pipeline executes most of the ALU operations, and includes a 32-bit barrel shifter. It consists of three pipeline stages:

Introduction

MAC pipe

The MAC pipeline executes all of the enhanced multiply, and multiply-accumulate instructions.

The MAC unit consists of a 32x16 multiplier and an accumulate unit that is configured to calculate the sum of two 16x16 multiplies. The accumulate unit has its own dedicated single register read port for the accumulate operand.

To minimize power consumption, the processor only clocks each of the MAC and ALU stages when required.

Return stack

The processor includes a three-entry return stack to accelerate returns from procedure calls. For each procedure call, the processor pushes the return address onto a hardware stack. When the processor recognizes a procedure return, the processor pops the address held in the return stack that the prefetch unit uses as the predicted return address.

Note

See Pipeline stages on page 1-24 for details of the pipeline stages and instruction progression.

See Chapter 3 System Control Coprocessor for system control coprocessor programming information.

1.5.2Load Store Unit (LSU)

The Load Store Unit (LSU) manages all load and store operations. The load-store pipeline decouples loads and stores from the MAC and ALU pipelines.

When the processor issues LDM and STM instructions to the LSU pipeline, other instructions run concurrently, subject to the requirements of supporting precise exceptions.

1.5.3Prefetch unit

The prefetch unit fetches instructions from the instruction cache, Instruction TCM, or from external memory and predicts the outcome of branches in the instruction stream.

See Chapter 5 Program Flow Prediction for more details.

Branch prediction

The core uses both static and dynamic branch prediction. All branches are predicted where the target address is an immediate address, or fixed-offset PC-relative address.

The first level of branch prediction is dynamic, through a 128-entry Branch Target Address Cache (BTAC). If the PC of a branch matches an entry in the BTAC, the processor uses the branch history and the target address to fetch the new instruction stream.