Unaligned and Mixed-endian Data Access Support

4.5Mixed-endian access support

The following sections describe mixed-endian data access:

•Legacy fixed instruction and data endianness

•ARMv6 support for mixed-endian data

•Instructions to change the CPSR E bit on page 4-21.

For more information, see The ARM Architecture Reference Manual.

4.5.1Legacy fixed instruction and data endianness

Prior to ARMv6 the endianness of both instructions and data are locked together, and the configuration of the processor and the external memory system must either be hard-wired or programmed in the first few instructions of the bootstrap code.

Where the endianness is configurable under program control, the MMU provides a mechanism in CP15 c1 to set the B bit, that enables byte addressing renaming with 32-bit words. This model of big-endian access, called BE-32 in this document, relies on a word-invariant view of memory where an aligned 32-bit word reads and writes the same word of data in memory when configured as either big-endian or little-endian.

For more information, see Endianness on page 8-42.

This behavior is still provided for legacy software when the U bit in CP15 Register c1 is zero, as Table 4-4 lists.

Table 4-4 Legacy endianness using CP15 c1

4.5.2ARMv6 support for mixed-endian data

In ARMv6 the instruction and data endianness are separated:

•instructions are fixed little-endian

•data accesses can be either little-endian or big-endian as controlled by bit 9, the E bit, of the Program Status Register.

The value of the E bit on any exception entry, including reset, is determined by the CPSR

Register 15 EE bit.

Fixed little-endian Instructions

Instructions must be naturally aligned and are always treated as being stored in memory in little-endian format. That is, the PC points to the least-significant-byte of the instruction.

Instructions must be treated as data by exception handlers, decoding SVC calls and Undefined instructions, for example.

Instructions can also be written as data by debuggers, Just-In-Time (JIT) compilers, or in operating systems that update exception vectors.

Unaligned and Mixed-endian Data Access Support

Mixed-endian data access

The operating-system typically has a required endian representation of internal data structures, but applications and device drivers have to work with data shared with other processors, DSP or DMA interfaces, that might have fixed big-endian or little-endian data formatting.

A byte-invariant addressing mechanism is provided that enables the load/store architecture to be qualified by the CPSR E bit that provides byte reversing of big-endian data in to, and out of, the processor register bank transparently. This byte-invariant big-endian representation is referred to as BE-8 in this document.

Mixed-endian configuration supported on page 4-19 describes the effect on byte, halfword, word, and multi-word accesses of setting the CPSR E bit when the U bit enables unaligned support.

Byte data access

The same physical byte in memory is accessed whether big-endian, BE-8, or little-endian:

•unsigned byte load as Load unsigned byte, endian independent on page 4-6 describes

•signed byte load as Load signed byte, endian independent on page 4-6 describes

•byte store as Store byte, endian independent on page 4-6 describes.

Halfword data access

The same two physical bytes in memory are accessed whether big-endian, BE-8, or little-endian. Big-endian halfword load data is byte-reversed as read into the processor register to ensure little-endian internal representation, and similarly is byte-reversed on store to memory:

•unsigned halfword load as Load unsigned halfword, little-endian on page 4-7, LE, and

Load unsigned halfword, big-endian on page 4-7, BE-8 describe

•signed halfword load as Load signed halfword, little-endian on page 4-8, LE, and Load signed halfword, big-endian on page 4-8, BE-8 describe

•halfword store as Store halfword, little-endian on page 4-9, LE, and Store halfword, big-endian on page 4-9, BE-8 describe.

Word data access

The same four physical bytes in memory are accessed whether big-endian, BE-8, or little-endian. Big-endian word load data is byte reversed as read into the processor register to ensure little-endian internal representation, and similarly is byte-reversed on store to memory:

•word load as Load word, little-endian on page 4-10, LE, and Load word, big-endian on page 4-10, BE-8 describes

•word store as Store word, little-endian on page 4-11, LE, and Store word, big-endian on page 4-11, BE-8 describes.

Unaligned and Mixed-endian Data Access Support

Mixed-endian configuration supported

This behavior is enabled when the U bit in CP15 Register c1 is set. This is only supported when the B bit in CP15 Register c1 is reset, as Table 4-5 lists.

4.5.3Reset values of the U, B, and EE bits

Table 4-6 lists the reset values of the BIGENDINIT and UBITINIT pins that determine the values of the U, B, and EE bits at reset. The pins determine the reset value of the B bit and both the Secure and Non-secure reset values of the U and EE bits.

Table 4-6 B bit, U bit, and EE bit settings

Unaligned and Mixed-endian Data Access Support

4.6Instructions to reverse bytes in a general-purpose register

When an application or device driver has to interface to memory-mapped peripheral registers or shared-memory DMA structures that are not the same endianness as that of the internal data structures, or the endianness of the Operating System, an efficient way of being able to explicitly transform the endianness of the data is required. The following new instructions are added to the ARM and Thumb instruction sets to provide this functionality:

•reverse word, 4 bytes, register, for transforming big and little-endian 32-bit representations

•reverse halfword and sign-extend, for transforming signed 16-bit representations

•Reverse packed halfwords in a register for transforming bigand little-endian 16-bit representations.

ARM1176JZ-S instruction set summary on page 1-30 describes these instructions.

4.6.1All load and store operations

All load and store instructions take account of the CPSR E bit. Data is transferred directly to registers when E = 0, and byte reversed if E = 1 for halfword, word, or multiple word transfers. Operation:

When CPSR[<E-bit>] = 1 then byte reverse load/store data