Vectored Interrupt Controller Port

12.2About the processor VIC port

Figure 12-1 shows the VIC port and the Peripheral Interface connecting a PL192 VIC and the processor.

IRQADDRV VICIRQADDRV

IRQADDR[31:2] VICVECTADDROUT[31:2] VICVECTADDRIN[31:0]

Figure 12-1 Connection of a VIC to the processor

Note

Do not be confused by the naming of the IRQADDRVSYNCEN and nVICSYNCEN signals. Although one is active HIGH and the other is active LOW they are connected to a common external synchronization disable signal. See the signal descriptions in Table 12-1 for more information.

The VIC port enables the processor to read the vector address as part of the IRQ interrupt entry. That is, the processor takes a vector address from this interface instead of using the legacy 0x00000018 or 0xFFFF0018.The VIC port does not support the reading of FIQ vector addresses.

The interrupt interface is designed to handle interrupts asserted by a controller that is clocked either synchronously or asynchronously to the processor clock. This capability ensures that the controller can be used in systems that have either a synchronous or asynchronous interface between the core clock and the AXI clock.

The VIC port consists of the signals that Table 12-1 lists.

IRQACK is driven by the processor to indicate to an external VIC that the processor wants to read the IRQADDR input.

Vectored Interrupt Controller Port

IRQADDRV is driven by a VIC to tell the processor that the address on the IRQADDR bus is valid and being held, and so it is safe for the processor to sample it.

IRQACK and IRQADDRV together implement a four-phase handshake between the processor and a VIC. See Timing of the VIC port on page 12-5 for more details.

12.2.1Synchronization of the VIC port signals

The AHB system bus clock signal HCLK can run at any frequency, synchronously or asynchronously to the processor clock signal, CLKIN. The processor VIC port can cope with any clocking mode.

nFIQ and nIRQ can be connected to either synchronous or asynchronous sources.

Synchronizers are provided internally for the case of asynchronous sources. The Synchronous Interrupt Enable port, INTSYNCEN, is also provided to enable SoC designers to bypass the

synchronizers if required. Similarly, a synchronizer is provided inside the processor for the IRQADDRV signal. If this signal is known to be synchronous, the synchronizer can be bypassed by pulling IRQADDRVSYNCEN HIGH.

These signals enable SoC designers to reduce interrupt latency if it is known that the nFIQ, nIRQ, or IRQADDRV input is always driven by a synchronous source. When connecting the PL192 VIC to the processor, INTSYNCEN must be tied LOW regardless of the clocking mode. This is because the PL192 nVICIRQ and nVICFIQ outputs are completely asynchronous,

because there are combinational paths that cross this device through to these outputs. However, IRQADDRVSYNCEN must be set depending on the clocking mode.

12.2.2Interrupt handler exit

The software acknowledges an IRQ interrupt handler exit to a VIC by issuing a write to the vector address register.