Debug

13.14 Monitor debug-mode debugging

Monitor debug-mode debugging is essential in real-time systems when the integer core cannot be halted to collect information. Engine controllers and servo mechanisms in hard drive controllers are examples of systems that might not be able to stop the code without physically damaging components. These are typical systems that can be debugged using Monitor debug-mode.

For situations that can only tolerate a small intrusion into the instruction stream, Monitor debug-mode is ideal. Using this technique, code can be suspended with an exception long enough to save off state information and important variables. The code continues when the exception handler is finished. The IFSR and DFSR indicate whether a debug exception has occurred, and if it has, the Method Of Entry (MOE) bits in the DSCR can be read to determine what caused the exception.

When in Monitor debug-mode, all breakpoint and watchpoint registers can be read and written with MRC and MCR instructions from a privileged processing mode.

13.14.1 Entering the debug monitor target

No debug-mode is the selected default by on power-on reset. Monitor debug-mode must be selected after reset by setting DSCR[15]. See CP14 c1, Debug Status and Control Register (DSCR) on page 13-7. When a software debug event occurs, as Software debug event on

page 13-32 describes, and Monitor debug-mode is selected and enabled, then a Debug exception is taken, although Prefetch Abort and Data Abort vector catch debug events are ignored. Debug exception on page 13-35 describes debug exception entry. The Prefetch Abort handler can check the IFSR, and the Data Abort handler can check the DFSR, to find out the caused of the exception. If the cause was a Debug exception, the handler branches to the debug monitor target. When the debug monitor target is running, it can determine and modify the processor state and new software debug events can be programmed.

13.14.2 Setting breakpoints, watchpoints, and vector catch debug events

When the debug monitor target is running, breakpoints, watchpoints, and vector catch debug events can be set. This can be done by executing MCR instructions to program the appropriate CP14 debug registers. The debug monitor target can only program these registers if the processor is in a privileged mode and Monitor debug-mode is selected and enabled, see Debug Status and Control Register bit field definitions on page 13-8.You can program a vector catch debug event using CP14 Debug Vector Catch Register.

You can program a breakpoint debug event using CP14 Debug Breakpoint Value Registers and CP14 Debug Breakpoint Control Registers, see CP14 c64-c69, Breakpoint Value Registers (BVR) on page 13-16 and CP14 c80-c85, Breakpoint Control Registers (BCR) on

page 13-17.You can program a watchpoint debug event using CP14 Debug Watchpoint Value Registers and CP14 Debug Watchpoint Control Registers, see CP14 c96-c97, Watchpoint Value Registers (WVR) on page 13-20, and CP14 c112-c113, Watchpoint Control Registers (WCR) on page 13-21.

Setting a simple breakpoint on an IMVA

You can set a simple breakpoint on an IMVA as follows:

1.Read the BCR.

2.Clear the BCR[0] enable breakpoint bit in the read word and write it back to the BCR. Now the breakpoint is disabled.

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3.Write the IMVA to the BVR register.

4.Write to the BCR with its fields set as follows:

•BCR[22:21] meaning of BVR bit set to b00 or b10, to indicate that the value loaded into BVR is to be compared against the IMVA bus as a match or mismatch.

•BCR[20] enable linking bit cleared, to indicate that this breakpoint is not to be linked.

•BCR [15:14] Secure access BCR field as required.

•BCR[8:5] byte address select BCR field as required.

•BCR[2:1] supervisor access BCR field as required.

•BCR[0] enable breakpoint bit set.

Note

Any BVR can be compared against the IMVA bus.

Setting a simple breakpoint on a context ID value

A simple breakpoint on a context ID value can be set, using one of the context ID capable BRPs, as follows:

1.Read the BCR.

2.Clear the BCR[0] enable breakpoint bit in the read word and write it back to the BCR. Now the breakpoint is disabled.

3.Write the context ID value to the BVR register.

4.Write to the BCR with its fields set as follows:

•BCR[22:21] meaning of BVR bit set to b01, to indicate that the value loaded into BVR is to be compared against the CP15 Context Id Register c13.

•BCR[20] enable linking bit cleared, to indicate that this breakpoint is not to be linked.

•BCR [15:14] Secure access BCR field as required.

•BCR[8:5] byte address select BCR field set to b1111.

•BCR[2:1] supervisor access BCR field as required.

•BCR[0] enable breakpoint bit set.

Note

Any BVR can be compared against the IMVA bus.

Setting a linked breakpoint

In the following sequence b is any of the breakpoint registers pairs with context ID comparison capability, and a is any of the implemented breakpoints different from b. You can link IMVA holding and contextID-holding breakpoints register pairs as follows:

1.Read the BCRa and BCRb.

2.Clear the BCRa[0] and BCRb[0] enable breakpoint bits in the read words and write them back to the BCRs. Now the breakpoints are disabled.

3.Write the IMVA to the BVRa register.

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4.Write the context ID to the BVRb register.

5.Write to the BCRb with its fields set as follows:

•BCRb[22:21] meaning of BVR bit set to b01, to indicate that the value loaded into BVRb is to be compared against the CP15 context ID register 13

•BCRb[20] enable linking bit, set

•BCR [15:14] Secure access set to b00.

•BCRb[8:5] byte address select set to b1111

•BCRb[2:1] supervisor access set to b11

•BCRb[0] enable breakpoint bit set.

6.Write to the BCRa with its fields set as follows:

•BCRa[22:21] meaning of BVR bit set to b00 or b10, to indicate that the value loaded into BVRa is to be compared against the IMVA bus as a match or mismatch

•BCRa[20] enable linking bit set, to link this BRP with the one indicated by BCRa[19:16], BRPb in this example

•BCR [15:14] Secure access as required.

•binary representation of b into BCR[9:6] linked BRP field

•BCRa[8:5] byte address select field as required

•BCRa[2:1] supervisor access field as required

•BCRa[0] enable breakpoint set.

Setting a simple watchpoint

You can set a simple watchpoint as follows:

1.Read the WCR.

2.Clear the WCR[0] enable watchpoint bit in the read word and write it back to the WCR. Now the watchpoint is disabled.

3.Write the DMVA to the WVR register.

4.Write to the WCR with its fields set as follows:

•WCR[20] enable linking bit cleared, to indicate that this watchpoint is not to be linked

•WCR byte address select, load/store access, Secure access field, and supervisor access fields as required

•WCR[0] enable watchpoint bit set.

Note

Any WVR can be compared against the DMVA bus.

Setting a linked watchpoint

In the following sequence b is any of the BRPs with context ID comparison capability. You can use any of the WRPs. You can link WRPs and contextID-holding BRPs as follows:

1.Read the WCR and BCRb.

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2.Clear the WCR[0] Enable Watchpoint and the BCRb[0] Enable breakpoint bits in the read words and write them back to the WCR and BCRb. Now the watchpoint and the breakpoint are disabled.

3.Write the DMVA to the WVR register.

4.Write the context ID to the BVRb register.

5.Write to the WCR with its fields set as follows:

•WCR[20] enable linking bit set, to link this WRP with the BRP indicated by WCR[19:16], BRPb in this example

•Binary representation of b into WCR[19:6] linked BRP field

•WCR byte address select, load/store access, Secure access field, and supervisor access fields as required

•WCR[0] enable watchpoint bit set.

6.Write to the BCRb with its fields set as follows:

•BCRb[22:21] meaning of BVR bit set to b01, to indicate that the value loaded into BVRb is to be compared against the CP15 Context ID Register.

•BCRb[20] enable linking bit, set

•BCR [15:14] Secure access set to b00

•BCRb[8:5] byte address select set to b1111

•BCRb[2:1] supervisor access set to b11

•BCRb[0] enable breakpoint bit set.

13.14.3Setting software breakpoint debug events (BKPT)

To set a software breakpoint on a particular virtual address, the debug monitor target must perform the following steps:

1.Read memory location and save actual instruction.

2.Write BKPT instruction to the memory location.

3.Read memory location again to check that the BKPT instruction has been written.

4.If it has not been written, determine the reason.

Note

Cache coherency issues might arise when writing a BKPT instruction. See Debugging in a cached system on page 13-43.

13.14.4 Using the debug communications channel

To read a word sent by a DBGTAP debugger:

1.Read the DSCR register.

2.If DSCR[30] rDTRfull flag is clear, then go to 1.

3.Read the word from the rDTR, CP14 Debug Register c5. To write a word for a DBGTAP debugger:

1.Read the DSCR register.

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2.If DSCR[29] wDTRfull flag is set, then go to 1.

3.Write the word to the wDTR, CP14 Debug Register c5.