List of Figures

Key to timing diagram conventions .............................................................................................

. xxi

Figure 1-1

ARM1176JZ-S processor block diagram ....................................................................................

1-8

Figure 1-2

ARM1176JZ-S pipeline stages .................................................................................................

1-24

Figure 1-3

Typical operations in pipeline stages ........................................................................................

1-26

Figure 1-4

Typical ALU operation ...............................................................................................................

1-26

Figure 1-5

Typical multiply operation .........................................................................................................

1-27

Figure 1-6

Progression of an LDR/STR operation .....................................................................................

1-28

Figure 1-7

Progression of an LDM/STM operation .....................................................................................

1-28

Figure 1-8

Progression of an LDR that misses ..........................................................................................

1-29

Figure 2-1

Secure and Non-secure worlds ...................................................................................................

2-3

Figure 2-2

Memory in the Secure and Non-secure worlds ...........................................................................

2-6

Figure 2-3

Memory partition in the Secure and Non-secure worlds .............................................................

2-7

Figure 2-4

Big-endian addresses of bytes within words .............................................................................

2-15

Figure 2-5

Little-endian addresses of bytes within words ..........................................................................

2-15

Figure 2-6

Register organization in ARM state ..........................................................................................

2-20

Figure 2-7

Processor core register set showing banked registers .............................................................

2-21

Figure 2-8

Register organization in Thumb state .......................................................................................

2-22

Figure 2-9

ARM state and Thumb state registers relationship ...................................................................

2-23

Figure 2-10

Program status register .............................................................................................................

2-24

Figure 2-11

LDREXB instruction ..................................................................................................................

2-30

Figure 2-12

STREXB instructions ................................................................................................................

2-30

Figure 2-13

LDREXH instruction ..................................................................................................................

2-31

Figure 2-14

STREXH instruction ..................................................................................................................

2-32

Figure 2-15

LDREXD instruction ..................................................................................................................

2-33

Figure 2-16

STREXD instruction ..................................................................................................................

2-33

Figure 2-17

CLREX instruction .....................................................................................................................

2-34

Figure 2-18

NOP-compatible hint instruction ...............................................................................................

2-34

Figure 3-1

System control and configuration registers .................................................................................

3-5

Figure 3-2

MMU control and configuration registers ....................................................................................

3-7

Figure 3-3

Cache control and configuration registers ..................................................................................

3-8

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List of Figures

Figure 3-4

TCM control and configuration registers ..............................................................................

....... 3-8

Figure 3-5

Cache Master Valid Registers .........................................................................................

........... 3-9

Figure 3-6

DMA control and configuration registers ..............................................................................

....... 3-9

Figure 3-7

System performance monitor registers .................................................................................

.... 3-10

Figure 3-8

System validation registers .......................................................................................................

3-11

Figure 3-9

CP15 MRC and MCR bit pattern .........................................................................................

...... 3-12

Figure 3-10

Main ID Register format ............................................................................................................

3-20

Figure 3-11

Cache Type Register format ..........................................................................................

........... 3-22

Figure 3-12

TCM Status Register format ..........................................................................................

........... 3-24

Figure 3-13

TLB Type Register format .........................................................................................................

3-25

Figure 3-14

Processor Feature Register 0 format .................................................................................

....... 3-27

Figure 3-15

Processor Feature Register 1 format .................................................................................

....... 3-28

Figure 3-16

Debug Feature Register 0 format .....................................................................................

........ 3-29

Figure 3-17

Memory Model Feature Register 0 format ..............................................................................

.. 3-31

Figure 3-18

Memory Model Feature Register 1 format ..............................................................................

.. 3-32

Figure 3-19

Memory Model Feature Register 2 format ..............................................................................

.. 3-34

Figure 3-20

Memory Model Feature Register 3 format ..............................................................................

.. 3-36

Figure 3-21

Instruction Set Attributes Register 0 format ........................................................................

...... 3-37

Figure 3-22

Instruction Set Attributes Register 1 format ........................................................................

...... 3-38

Figure 3-23

Instruction Set Attributes Register 2 format ........................................................................

...... 3-39

Figure 3-24

Instruction Set Attributes Register 3 format ........................................................................

...... 3-41

Figure 3-25

Instruction Set Attributes Register 4 format ........................................................................

...... 3-42

Figure 3-26

Control Register format .............................................................................................................

3-45

Figure 3-27

Auxiliary Control Register format ...................................................................................

........... 3-49

Figure 3-28

Coprocessor Access Control Register format ..........................................................................

. 3-51

Figure 3-29

Secure Configuration Register format ................................................................................

....... 3-52

Figure 3-30

Secure Debug Enable Register format .................................................................................

.... 3-54

Figure 3-31

Non-Secure Access Control Register format ...........................................................................

. 3-56

Figure 3-32

Translation Table Base Register 0 format ............................................................................

.... 3-58

Figure 3-33

Translation Table Base Register 1 format ............................................................................

.... 3-59

Figure 3-34

Translation Table Base Control Register format ......................................................................

. 3-61

Figure 3-35

Domain Access Control Register format ...............................................................................

.... 3-63

Figure 3-36

Data Fault Status Register format ...................................................................................

.......... 3-64

Figure 3-37

Instruction Fault Status Register format ............................................................................

........ 3-66

Figure 3-38

Cache operations ......................................................................................................................

3-70

Figure 3-39

Cache operations with MCRR instructions .............................................................................

.. 3-71

Figure 3-40

c7 format for Set and Index .......................................................................................................

3-72

Figure 3-41

c7 format for MVA .....................................................................................................................

3-73

Figure 3-42

Format of c7 for VA ...................................................................................................................

3-74

Figure 3-43

Cache Dirty Status Register format ..................................................................................

........ 3-78

Figure 3-44

c7 format for Flush Branch Target Entry using MVA ................................................................

3-79

Figure 3-45

PA Register format for successful translation .......................................................................

.... 3-80

Figure 3-46

PA Register format for aborted translation ..........................................................................

...... 3-81

Figure 3-47

TLB Operations Register MVA and ASID format ......................................................................

3-88

Figure 3-48

TLB Operations Register ASID format .................................................................................

..... 3-88

Figure 3-49

Instruction and data cache lockdown register formats .....................................................

......... 3-88

Figure 3-50

Data TCM Region Register format .....................................................................................

....... 3-91

Figure 3-51

Instruction TCM Region Register format ..............................................................................

..... 3-92

Figure 3-52

Data TCM Non-secure Control Access Register format ...........................................................

3-94

Figure 3-53

Instruction TCM Non-secure Control Access Register format ..................................................

3-96

Figure 3-54

TCM Selection Register format .......................................................................................

.......... 3-97

Figure 3-55

Cache Behavior Override Register format .............................................................................

... 3-98

Figure 3-56

TLB Lockdown Register format ........................................................................................

....... 3-100

Figure 3-57

Primary Region Remap Register format ................................................................................

. 3-102

Figure 3-58

Normal Memory Remap Register format ................................................................................

3-103

Figure 3-59

DMA identification and status registers format ......................................................................

. 3-106

Figure 3-60

DMA User Accessibility Register format ..............................................................................

... 3-107

Figure 3-61

DMA Channel Number Register format ..................................................................................

3-109

Figure 3-62

DMA Control Register format .........................................................................................

......... 3-112

Figure 3-63

DMA Channel Status Register format ..................................................................................

... 3-117

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List of Figures

Figure 3-64

DMA Context ID Register format ......................................................................................

...... 3-120

Figure 3-65

Secure or Non-secure Vector Base Address Register format ................................................

3-121

Figure 3-66

Monitor Vector Base Address Register format ........................................................................

3-122

Figure 3-67

Interrupt Status Register format ..............................................................................................

3-124

Figure 3-68

FCSE PID Register format ......................................................................................................

3-125

Figure 3-69

Address mapping with the FCSE PID Register .......................................................................

3-127

Figure 3-70

Context ID Register format .....................................................................................................

3-127

Figure 3-71

Peripheral Port Memory Remap Register format ....................................................................

3-130

Figure 3-72

Secure User and Non-secure Access Validation Control Register format ..............................

3-132

Figure 3-73

Performance Monitor Control Register format ........................................................................

3-133

Figure 3-74

System Validation Counter Register format for external debug request counter .............

....... 3-141

Figure 3-75

System Validation Cache Size Mask Register format .............................................................

3-145

Figure 3-76

TLB Lockdown Index Register format ..................................................................................

... 3-149

Figure 3-77

TLB Lockdown VA Register format .....................................................................................

.... 3-149

Figure 3-78

TLB Lockdown PA Register format .....................................................................................

.... 3-150

Figure 3-79

TLB Lockdown Attributes Register format .............................................................................

. 3-151

Figure 4-1

Load unsigned byte .....................................................................................................................

4-6

Figure 4-2

Load signed byte .........................................................................................................................

4-6

Figure 4-3

Store byte ....................................................................................................................................

4-7

Figure 4-4

Load unsigned halfword, little-endian ................................................................................

......... 4-7

Figure 4-5

Load unsigned halfword, big-endian ...................................................................................

........ 4-8

Figure 4-6

Load signed halfword, little-endian ..................................................................................

........... 4-8

Figure 4-7

Load signed halfword, big-endian .....................................................................................

.......... 4-9

Figure 4-8

Store halfword, little-endian ........................................................................................................

4-9

Figure 4-9

Store halfword, big-endian ........................................................................................................

4-10

Figure 4-10

Load word, little-endian .............................................................................................................

4-10

Figure 4-11

Load word, big-endian ..............................................................................................................

4-11

Figure 4-12

Store word, little-endian ............................................................................................................

4-11

Figure 4-13

Store word, big-endian ..............................................................................................................

4-12

Figure 6-1

Memory ordering restrictions .........................................................................................

........... 6-24

Figure 6-2

Translation table managed TLB fault checking sequence part 1 ...........................................

... 6-30

Figure 6-3

Translation table managed TLB fault checking sequence part 2 ...........................................

... 6-31

Figure 6-4

Backwards-compatible first-level descriptor format ..................................................................

6-37

Figure 6-5

Backwards-compatible second-level descriptor format .............................................................

6-38

Figure 6-6

Backwards-compatible section, supersection, and page translation .....................................

... 6-38

Figure 6-7

ARMv6 first-level descriptor formats with subpages disabled ................................................

... 6-39

Figure 6-8

ARMv6 second-level descriptor format .................................................................................

.... 6-40

Figure 6-9

ARMv6 section, supersection, and page translation .................................................................

6-41

Figure 6-10

Creating a first-level descriptor address ...........................................................................

........ 6-44

Figure 6-11

Translation for a 1MB section, ARMv6 format .........................................................................

. 6-46

Figure 6-12

Translation for a 1MB section, backwards-compatible format ..................................................

6-46

Figure 6-13

Generating a second-level page table address ........................................................................

6-47

Figure 6-14

Large page table walk, ARMv6 format .................................................................................

..... 6-48

Figure 6-15

Large page table walk, backwards-compatible format ...........................................................

... 6-49

Figure 6-16

4KB small page or 1KB small subpage translations, backwards-compatible format ................

6-50

Figure 6-17

4KB extended small page translations, ARMv6 format .............................................................

6-51

Figure 6-18

4KB extended small page or 1KB extended small subpage translations,

backwards-compatible format ...................................................................................................

6-52

Figure 7-1

Level one cache block diagram ........................................................................................

.......... 7-4

Figure 8-1

Level two interconnect interfaces ....................................................................................

............ 8-2

Figure 8-2

Channel architecture of reads ........................................................................................

............. 8-8

Figure 8-3

Channel architecture of writes .......................................................................................

............. 8-8

Figure 8-4

Swizzling of data and strobes in BE-32 big-endian configuration ..........................................

... 8-42

Figure 9-1

Processor clocks with no IEM .........................................................................................

............ 9-3

Figure 9-2

Read latency with no IEM ...........................................................................................................

9-4

Figure 9-3

Processor clocks with IEM ..........................................................................................................

9-6

Figure 9-4

Processor synchronization with IEM ...................................................................................

........ 9-6

Figure 9-5

Read latency with IEM ................................................................................................................

9-8

Figure 9-6

Power-on reset ..........................................................................................................................

9-10

Figure 10-1

IEM structure .............................................................................................................................

10-7

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List of Figures

Figure 11-1

Core and coprocessor pipelines ......................................................................................

......... 11-5

Figure 11-2

Coprocessor pipeline and queues .....................................................................................

....... 11-5

Figure 11-3

Coprocessor pipeline ................................................................................................................

11-7

Figure 11-4

Token queue buffers .................................................................................................................

11-9

Figure 11-5

Queue reading and writing ......................................................................................................

11-10

Figure 11-6

Queue flushing ........................................................................................................................

11-11

Figure 11-7

Instruction queue ....................................................................................................................

11-12

Figure 11-8

Coprocessor data transfer ......................................................................................................

11-15

Figure 11-9

Instruction iteration for loads ...................................................................................................

11-16

Figure 11-10

Load data buffering .................................................................................................................

11-17

Figure 12-1

Connection of a VIC to the processor ................................................................................

....... 12-3

Figure 12-2

VIC port timing example ............................................................................................................

12-5

Figure 12-3

Interrupt entry sequence ...........................................................................................................

12-7

Figure 13-1

Typical debug system ...............................................................................................................

13-2

Figure 13-2

Debug ID Register format .........................................................................................................

13-6

Figure 13-3

Debug Status and Control Register format ............................................................................

... 13-8

Figure 13-4

DTR format .............................................................................................................................

13-12

Figure 13-5

Vector Catch Register format ..................................................................................................

13-13

Figure 13-6

Breakpoint Control Registers format .................................................................................

...... 13-17

Figure 13-7

Watchpoint Control Registers format .................................................................................

..... 13-21

Figure 14-1

JTAG DBGTAP state machine diagram ...................................................................................

. 14-2

Figure 14-2

RealView ICE clock synchronization ..................................................................................

....... 14-3

Figure 14-3

Bypass register bit order ...........................................................................................................

14-8

Figure 14-4

Device ID code register bit order ...................................................................................

........... 14-9

Figure 14-5

Instruction register bit order ......................................................................................................

14-9

Figure 14-6

Scan chain select register bit order ................................................................................

......... 14-10

Figure 14-7

Scan chain 0 bit order .............................................................................................................

14-11

Figure 14-8

Scan chain 1 bit order .............................................................................................................

14-11

Figure 14-9

Scan chain 4 bit order .............................................................................................................

14-13

Figure 14-10

Scan chain 5 bit order, EXTEST selected ............................................................................

... 14-15

Figure 14-11

Scan chain 5 bit order, INTEST selected ............................................................................

.... 14-15

Figure 14-12

Scan chain 6 bit order .............................................................................................................

14-17

Figure 14-13

Scan chain 7 bit order .............................................................................................................

14-18

Figure 14-14

Behavior of the ITRsel IR instruction ..............................................................................

........ 14-22

Figure 15-1

ETMCPADDRESS format .................................................................................................

........ 15-7

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