System Control Coprocessor

3.2.42c11, DMA Context ID Register

The DMA Context ID Register for each channel contains the processor 32-bit Context ID of the process that uses that channel.

The DMA Context ID Register is:

•in CP15 c11

•a 32-bit read/write register for each DMA channel common to Secure and Non-secure worlds

•accessible in privileged modes only.

Figure 3-64 shows the arrangement of bits in the DMA Context ID Register.

Figure 3-64 DMA Context ID Register format

Table 3-119 lists how the bit values correspond with the DMA Context ID Register functions.

Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control Register on page 3-55. Table 3-120 lists the results of attempted access for each mode.

Table 3-120 Results of access to the DMA Context ID Register

To access the DMA Context ID register in a privileged mode set the DMA Channel Number

Register to the appropriate DMA channel and read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c11

•CRm set to c15

•Opcode_2 set to 0.

System Control Coprocessor

As part of the initialization of the DMA channel, the process that uses that channel writes the processor Context ID to the DMA Context ID Register. Where the channel is designated as a User-accessible channel, the privileged process, that initializes the channel for use in User mode, must write the Context ID at the same time that the software writes to the U bit for the channel.

The process that translates VAs to physical addresses uses the ASID stored in the bottom eight bits of the Context ID register to enable different VA maps to co-exist. Attempts to write this register while the DMA channel is Running or Queued has no effect.

Only privileged processes can read this register. This provides anonymity of the DMA channel usage from User processes. On a context switch, where the state of the DMA is stacked and restored, the saved state must include this register.

If a user process attempts to access this privileged register the processor takes an Undefined instruction trap.

3.2.43c12, Secure or Non-secure Vector Base Address Register

The purpose of the Secure or Non-secure Vector Base Address Register is to hold the base address for exception vectors in the Secure and Non-secure worlds. For more information, see Exceptions on page 2-36.

The Secure or Non-secure Vector Base Address Register is:

•in CP15 c12

•a 32-bit read/write register banked in Secure and Non-secure worlds

•accessible in privileged modes only.

Figure 3-65 shows the arrangement of bits in the register.

Figure 3-65 Secure or Non-secure Vector Base Address Register format

Table 3-121 lists how the bit values correspond with the Secure or Non-secure Vector Base

Address Register functions.

Table 3-121 Secure or Non-secure Vector Base Address Register bit functions

When an exception occurs in the Secure world, the core branches to address:

Secure Vector_Base_Address + Exception_Vector_Address.

When an exception occurs in the Non-secure world, the core branches to address:

Non-secure Vector_Base_Address + Exception_Vector_Address.

When high vectors are enabled, regardless of the value of the register the core branches to:

System Control Coprocessor

0xFFFF0000 + Exception_Vector_Address

You can configure IRQ, FIQ, and External abort exceptions to branch to Secure Monitor mode, see c1, Secure Configuration Register on page 3-52. In this case the processor uses the Monitor Vector Base Address, see c12, Monitor Vector Base Address Register, to calculate the branch address. The Reset exception always branches to 0x00000000, regardless of the value of the Vector Base Address except when the processor uses high vectors.

Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9.

Table 3-122 lists the results of attempted access for each mode.

Table 3-122 Results of access to the Secure or Non-secure Vector Base Address Register

To use the Secure or Non-secure Vector Base Address Register read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c12

•CRm set to c0

•Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c12, c0, 0 ; Read Secure or Non-secure Vector Base Address Register MCR p15, 0, <Rd>, c12, c0, 0 ; Write Secure or Non-secure Vector Base Address Register

3.2.44c12, Monitor Vector Base Address Register

The purpose of the Monitor Vector Base Address Register is to hold the base address for the

Secure Monitor exception vector. For more information, see Exceptions on page 2-36.

The Monitor Vector Base Address Register is:

•in CP15 c12

•a 32-bit read/write register in the Secure world only

•accessible in Secure privileged modes only.

Figure 3-66 shows the arrangement of bits in the register.

Figure 3-66 Monitor Vector Base Address Register format

System Control Coprocessor

Table 3-123 lists how the bit values correspond with the Monitor Vector Base Address Register functions.

When an exception branches to the Secure Monitor mode, the core branches to address:

Monitor_Base_Address + Exception_Vector_Address.

The Secure Monitor Call Exception caused by an SMC instruction branches to Secure Monitor mode. You can configure IRQ, FIQ, and External abort exceptions to branch to Secure Monitor mode, see c1, Secure Configuration Register on page 3-52. These are the only exceptions that can branch to Secure Monitor mode and that use the Monitor Vector Base Address Register to calculate the branch address. For more information about exceptions, see Exception vectors on page 2-48.

Note

The Monitor Vector Base Address Register is 0x00000000 at reset. The Secure boot code must program the register with an appropriate value for the Secure Monitor.

Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9.

Table 3-124 lists the results of attempted access for each mode.

Table 3-124 Results of access to the Monitor Vector Base Address Register

To use the Monitor Vector Base Address Register read or write CP15 with:

•Opcode_1 set to 0

•CRn set to c12

•CRm set to c0

•Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c12, c0, 1 ; Read Monitor Vector Base Address Register

MCR p15, 0, <Rd>, c12, c0, 1 ; Write Monitor Vector Base Address Register

3.2.45c12, Interrupt Status Register

The purpose of the Interrupt Status Register is to:

•reflect the state of the nFIQ and nIRQ pins on the processor

•to reflect the state of external aborts.

System Control Coprocessor

The Interrupt Status Register is:

•in CP15 c12

•a 32-bit read-only register common to Secure and Non-secure worlds

•accessible in privileged modes only.

Figure 3-67 shows the arrangement of bits in the register.

Figure 3-67 Interrupt Status Register format

Table 3-125 lists how the bit values correspond with the Interrupt Status Register functions.

Table 3-125 Interrupt Status Register bit functions

a. The reset values depend on external signals.

Note

•The F and I bits directly reflect the state of the nFIQ and nIRQ pins respectively, but are the inverse state.

•The A bit is set when an external abort occurs and automatically clears when the abort is taken.

Table 3-126 lists the results of attempted access for each mode.

Table 3-126 Results of access to the Interrupt Status Register

The A, I, and F bits map to the same format as the CPSR so that you can use the same mask for these bits.