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Level Two Interface

8.6Peripheral Interface transfers

The tables in this section describe the Peripheral Interface behavior for reads and writes for the following interface signals:

AxADDRP[31:0]

AxBURSTP[1:0]

AxSIZEP[2:0]

AxLENP[3:0]

WSTRBP[3:0], for write accesses.

See the AMBA AXI Protocol Specification for details of the other AXI signals.

Table 8-70 shows the values of AxADDRP, AxBURSTP, AxSIZEP, AxLENP, and WSTRBP for example Peripheral Interface reads and writes.

Table 8-70 Example Peripheral Interface reads and writes

Example transfer, read or write

AxADDRP

AxBURSTP

AxSIZEP

AxLENP

WSTRBP

 

 

 

 

 

 

Words 0-7

0x00

Incr

32-bit

2 data transfers

b1111

 

 

 

 

 

 

 

0x04

 

 

 

b1111

 

 

 

 

 

 

 

0x08

Incr

32-bit

2 data transfers

b1111

 

 

 

 

 

 

 

0x0C

 

 

 

b1111

 

 

 

 

 

 

 

0x10

Incr

32-bit

2 data transfers

b1111

 

 

 

 

 

 

 

0x14

 

 

 

b1111

 

 

 

 

 

 

 

0x18

Incr

32-bit

2 data transfers

b1111

 

 

 

 

 

 

 

0x1C

 

 

 

b1111

 

 

 

 

 

 

Words 0-3

0x00

Incr

32-bit

2 data transfers

b1111

 

 

 

 

 

 

 

0x04

 

 

 

b1111

 

 

 

 

 

 

 

0x08

Incr

32-bit

 

b1111

 

 

 

 

 

 

 

0x0C

 

 

 

b1111

 

 

 

 

 

 

Words 0-2

0x00

Incr

32-bit

2 data transfers

b1111

 

 

 

 

 

 

 

0x04

 

 

 

b1111

 

 

 

 

 

 

 

0x08

Incr

32-bit

1 data transfer

b1111

 

 

 

 

 

 

Words 0-1

0x00

Incr

32-bit

2 data transfers

b1111

 

 

 

 

 

 

 

0x04

 

 

 

b1111

 

 

 

 

 

 

Word 2

0x08

Incr

32-bit

1 data transfer

b1111

 

 

 

 

 

 

Word 0, bytes 0 and 1

0x00

Incr

16-bit

1 data transfer

b0011

 

 

 

 

 

 

Word 1, bytes 2 and 3

0x06

Incr

16-bit

1 data transfer

b1100

 

 

 

 

 

 

Word 2, byte 3

0x0B

Incr

8-bit

1 data transfer

b1000

 

 

 

 

 

 

The peripheral port can only do incrementing bursts of 2 data transfers maximum. It does not support unaligned accesses.

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Level Two Interface

8.7Endianness

ARM1176JZ-S processors can be configured in one of three endianness modes of operation using the U, B, and E bits of the CP15 c1 Control Register, see Mixed-endian access support on page 4-17.

BE-8 refers to byte-invariant big-endian configuration on 16-bit, halfword, and 32-bit, word, quantities only.

Even if the data and DMA ports are 64-bit wide, the accesses issued on these ports still have to be considered as two 32-bit accesses in parallel. The BE-8 configuration does not apply to the 64-bit data but on the two 32-bit words forming these 64-bit data.

The AXI protocol does not support 32-bit word-invariant big-endian, BE-32, accesses. Therefore, in this configuration the ARM1176JZ-S processor issues byte-invariant big-endian, BE-8, accesses on the four ports by swizzling the byte lanes and the byte strobes as Figure 8-4 shows.

DATA[63:56]

DATA[63:56]

DATA[55:48]

DATA[55:48]

DATA[47:40]

DATA[47:40]

DATA[39:32]

DATA[39:32]

DATA[31:24]

DATA[31:24]

DATA[23:16]

DATA[23:16]

DATA[15:8]

DATA[15:8]

DATA[7:0]

DATA[7:0]

STRB[7]

STRB[7]

STRB[6]

STRB[6]

STRB[5]

STRB[5]

STRB[4]

STRB[4]

STRB[3]

STRB[3]

STRB[2]

STRB[2]

STRB[1]

STRB[1]

STRB[0]

STRB[0]

Figure 8-4 Swizzling of data and strobes in BE-32 big-endian configuration

Note

If you want to configure the processor for BE-32 mode, it is strongly recommended that you use the BIGENDINIT and UBITINIT input pins. See c1, Control Register on page 3-44 bit [7].

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Level Two Interface

8.8Locked access

The AXI protocol specifies that, when a locked transaction occurs, the master must follow the locked transaction with an unlocked transaction to remove the lock of the interconnect. For ARM1176JZ-S processors, this implies that, in the case of an abort received on the read part of

a SWP instruction, the Peripheral port or Data port issues a dummy write access with all byte strobes LOW at the same address as the read access and with AWLOCK = 00, normal

transaction.

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