Programmer’s Model

2.9Registers

The processor has a total of 40 registers:

•33 general-purpose 32-bit registers

•seven 32-bit status registers.

These registers are not all accessible at the same time. The processor state and operating mode determine the registers that are available to the programmer.

2.9.1The ARM state core register set

In ARM state, 16 general registers and one or two status registers are accessible at any time. In privileged modes, mode-specific banked registers become available. Figure 2-6 on page 2-20 shows the registers that are available in each mode.

The ARM state core register set contains 16 directly-accessible registers, R0-R15. Another register, the Current Program Status Register (CPSR), contains condition code flags, status bits, and current mode bits. Registers R0-R12 are general-purpose registers used to hold either data or address values. Registers R13, R14, R15, and the Saved Program Status Register (SPSR) have the following special functions:

Stack Pointer Register R13 is used as the Stack Pointer (SP).

R13 is banked for the exception modes. This means that an exception handler can use a different stack to the one in use when the exception occurred.

In many instructions, you can use R13 as a general-purpose register, but the architecture deprecates this use of R13 in most instructions. For more information see the ARM Architecture Reference Manual.

Link Register Register R14 is used as the subroutine Link Register (LR).

Register R14 receives the return address when a Branch with Link (BL or

BLX) instruction is executed.

You can treat R14 as a general-purpose register at all other times. The corresponding banked registers R14_mon, R14_svc, R14_irq, R14_fiq, R14_abt, and R14_und are similarly used to hold the return values when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines.

Program Counter Register R15 holds the PC:

•in ARM state this is word-aligned

•in Thumb state this is halfword-aligned

•in Jazelle state this is byte-aligned.

Saved Program Status Register

In privileged modes, another register, the SPSR, is accessible. This contains the condition code flags, status bits, and current mode bits saved as a result of the exception that caused entry to the current mode.

Programmer’s Model

Banked registers have a mode identifier that indicates the mode that they relate to. Table 2-5 lists these mode identifiers.

Table 2-5 Register mode identifiers

a. The usr identifier is usually omitted from register names. It is only used in descriptions where the User or System mode register is specifically accessed from another operating mode.

FIQ mode has seven banked registers mapped to R8–R14 (R8_fiq–R14_fiq). As a result many FIQ handlers do not have to save any registers.

The Secure Monitor, Supervisor, Abort, IRQ, and Undefined modes each have alternative mode-specific registers mapped to R13 and R14, permitting a private stack pointer and link register for each mode.

Figure 2-6 on page 2-20 shows the ARM state registers.

= banked register

Figure 2-6 Register organization in ARM state

Figure 2-7 on page 2-21 shows an alternative view of the ARM registers.

Programmer’s Model

16 general purpose registers + 1 status register

2.9.2The Thumb state core register set

The Thumb state core register set is a subset of the ARM state set. The programmer has direct access to:

•eight general registers, R0–R7. For details of high register access in Thumb state see

Accessing high registers in Thumb state on page 2-22

•the PC

•a stack pointer, SP, ARM R13

•an LR, ARM R14

•the CPSR.

There are banked SPs, LRs, and SPSRs for each privileged mode. Figure 2-8 on page 2-22 shows the Thumb state core register set.