Preface
About this manual
This is for the ARM1176JZ-S processor. In this book the generic term processor means the
ARM1176JZ-S processor.
Product revision status
The rnpn identifier indicates the revision status of the product described in this manual, where:
rn |
Identifies the major revision of the product. |
pn |
Identifies the minor revision or modification status of the product. |
Intended audience
This document is written for hardware and software engineers implementing the processor system designs, and integrating the processor into a target system.
Using this manual
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the processor and descriptions of the major functional blocks.
Chapter 2 Programmer’s Model
Read this for a description of the processor registers and programming details.
Chapter 3 System Control Coprocessor
Read this for a description of the processor’s system control coprocessor CP15 registers and programming details.
Chapter 4 Unaligned and Mixed-endian Data Access Support
Read this for a description of the processor support for unaligned and mixed-endian data accesses.
Chapter 5 Program Flow Prediction
Read this for a description of the functions of the processor’s Prefetch Unit, including static and dynamic branch prediction and the return stack.
Chapter 6 Memory Management Unit
Read this for a description of the processor’s Memory Management Unit (MMU) and the address translation process.
Chapter 7 Level One Memory System
Read this for a description of the processor’s level one memory system, including caches, TCM, DMA, TLBs, and write buffer.
Chapter 8 Level Two Interface
Read this for a description of the processor’s level two memory interface and the peripheral port.
Chapter 9 Clocking and Resets
Read this for a description of the processor’s clocking modes and the reset signals.
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Preface
Chapter 10 Power Control
Read this for a description of the processor’s power control facilities.
Chapter 11 Coprocessor Interface
Read this for details of the processor’s coprocessor interface.
Chapter 12 Vectored Interrupt Controller Port
Read this for a description of the processor’s Vectored Interrupt Controller interface.
Chapter 13 Debug
Read this for a description of the processor’s debug support.
Chapter 14 Debug Test Access Port
Read this for a description of the JTAG-based processor Debug Test Access Port.
Chapter 15 Trace Interface Port
Read this for a description of the trace interface port.
Chapter 16 Cycle Timings and Interlock Behavior
Read this for a description of the processor’s instruction cycle timing and for details of the interlocks.
Chapter 17 AC Characteristics
Read this for a description of the timing parameters applicable to the processor.
Appendix A Signal Descriptions
Read this for a description of the processor signals.
Appendix B Summary of ARM1136J-S and ARM1176JZ-S Processor Differences
Read this for a summary of the differences between the ARM1136JF-S™ and
ARM1176JZ-S processors.
Appendix C Revisions
Read this for a description of the technical changes between released issues of this book.
Glossary Read this for definitions of terms used in this book.
Conventions
This section describes the conventions that this manual uses:
•Typographical
•Timing diagrams on page xxi
•Signals on page xxi
Typographical
The typographical conventions are:
italic |
Highlights important notes, introduces special terminology, denotes |
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internal cross-references, and citations. |
bold |
Highlights interface elements, such as menu names. Denotes signal |
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names. Also used for terms in descriptive lists, where appropriate. |
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monospace |
Denotes text that you can enter at the keyboard, such as commands, file |
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and program names, and source code. |
monospace |
Denotes a permitted abbreviation for a command or option. You can enter |
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the underlined text instead of the full command or option name. |
monospace italic |
Denotes arguments to monospace text where the argument is to be |
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replaced by a specific value. |
monospace bold |
Denotes language keywords when used outside example code. |
< and > |
Enclose replaceable terms for assembler syntax where they appear in code |
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or code fragments. For example: |
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MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2> |
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.
Clock
HIGH to LOW
Transient 
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Key to timing diagram conventions
Timing diagrams sometimes show single-bit signals as HIGH and LOW at the same time and they look similar to the bus change shown in Key to timing diagram conventions. If a timing diagram shows a single-bit signal in this way then its value does not affect the accompanying description.
Signals
The signal conventions are:
Signal level |
The level of an asserted signal depends on whether the signal is |
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active-HIGH or active-LOW. Asserted means: |
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• |
HIGH for active-HIGH signals |
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• |
LOW for active-LOW signals. |
Lower-case n |
At the start or end of a signal name denotes an active-LOW signal. |
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Additional reading
This section lists publications by ARM and by third parties.
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Preface
See Infocenter, http://infocenter.arm.com, for access to ARM documentation.
ARM publications
This book contains information that is specific to the ARM1176JZ-S processors. See the following documents for other relevant information:
•ARM Architecture Reference Manual (ARM DDI 0406)
Note
The ARM DDI 0406 edition of the ARM Architecture Reference Manual (the ARM ARM) incorporates the supplements to the previous ARM ARM, including the Security Extensions supplement.
•Jazelle® V1 Architecture Reference Manual (ARM DDI 0225)
•AMBA® AXI Protocol V1.0 Specification (ARM IHI 0022)
•Embedded Trace Macrocell Architecture Specification (ARM IHI 0014)
•ARM1136J-S Technical Reference Manual (ARM DDI 0211)
•ARM11 Memory Built-In Self Test Controller Technical Reference Manual
(ARM DDI 0289)
•ARM1176JZF-S™ and ARM1176JZ-S™ Implementation Guide (ARM DII 0081)
•CoreSight ETM11™ Technical Reference Manual (ARM DDI 0318)
•RealView™ Compilation Tools Developer Guide (ARM DUI 0203)
•ARM PrimeCell® Vectored Interrupt Controller (PL192) Technical Reference Manual
(ARM DDI 0273).
•Intelligent Energy Controller Technical Overview (ARM DTO 0005).
Other publications
This section lists relevant documents published by third parties:
•IEEE Standard Test Access Port and Boundary-Scan Architecture specification 1149.1-1990 (JTAG).
Figure 14-1 on page 14-2 is printed with permission IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 2001, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.
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