Programmer’s Model

2.10The program status registers

The processor contains one CPSR, and six SPSRs for exception handlers to use. The program status registers:

•hold information about the most recently performed ALU operation

•control the enabling and disabling of interrupts

•set the processor operating mode.

Figure 2-10 shows the arrangement of bits in the status registers, and the sections from The condition code flags to Reserved bits on page 2-29 inclusive describe it.

Figure 2-10 Program status register

Note

The bits that Figure 2-10 identifies as Do Not Modify (DNM), Read As Zero (RAZ), must not be modified by software. These bits are:

•Readable, to enable the processor state to be preserved, for example, during process context switches

•Writable, to enable the processor state to be restored. To maintain compatibility with future ARM processors, and as good practice, you are strongly advised to use a read-modify-write strategy when changing the CPSR.

2.10.1The condition code flags

The N, Z, C, and V bits are the condition code flags. You can set them by arithmetic and logical operations, and also by MSR and LDM instructions. The processor tests these flags to determine whether to execute an instruction.

In ARM state, most instructions can execute conditionally on the state of the N, Z, C, and V bits. The exceptions are:

•BKPT

•CDP2

•CPS

•LDC2

•MCR2

•MCRR2

•MRC2

•MRRC2

•PLD

Programmer’s Model

•SETEND

•RFE

•SRS

•STC2.

In Thumb state, only the Branch instruction can be executed conditionally. For more information about conditional execution, see the ARM Architecture Reference Manual.

2.10.2The Q flag

The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions:

•QADD

•QDADD

•QSUB

•QDSUB

•SMLAD

•SMLAxy

•SMLAWy

•SMLSD

•SMUAD

•SSAT

•SSAT16

•USAT

•USAT16.

The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.

To determine the status of the Q flag you must read the PSR into a register and extract the Q flag from this. For details of how the Q flag is set and cleared, see individual instruction definitions in the ARM Architecture Reference Manual.

2.10.3The J bit

The J bit in the CPSR indicates when the processor is in Jazelle state.

Note

•The combination of J = 1 and T = 1 causes similar effects to setting T=1 on a non Thumb-aware processor. That is, the next instruction executed causes entry to the Undefined Instruction exception. Entry to the exception handler causes the processor to re-enter ARM state, and the handler can detect that this was the cause of the exception because J and T are both set in SPSR_und.

•MSR cannot be used to change the J bit in the CPSR.

Programmer’s Model

•The placement of the J bit avoids the status or extension bytes in code running on ARMv5TE or earlier processors. This ensures that OS code written using the deprecated CPSR, SPSR, CPSR_all, or SPSR_all syntax for the destination of an MSR instruction continues to work.

2.10.4The GE[3:0] bits

Some of the SIMD instructions set GE[3:0] as greater-than-or-equal bits for individual halfwords or bytes of the result. Table 2-6 lists these.

Table 2-6 GE[3:0] settings

Note

GE bit is 1 if A op B ≥ C, otherwise 0.

The SEL instruction uses GE[3:0] to select the source register that supplies each byte of its result.

Note

•For unsigned operations, the GE bits are determined by the usual ARM rules for carries out of unsigned additions and subtractions, and so are carry-out bits.

•For signed operations, the rules for setting the GE bits are chosen so that they have the same sort of greater than or equal functionality as for unsigned operations.

Programmer’s Model

2.10.5The E bit

ARM and Thumb instructions are provided to set and clear the E-bit. The E bit controls load/store endianness. For details of where the E bit is used see Chapter 4 Unaligned and Mixed-endian Data Access Support.

Architecture versions prior to ARMv6 specify this bit as SBZ. This ensures no endianness reversal on loads or stores.

2.10.6The A bit

The A bit is set automatically. It is used to disable imprecise Data Aborts. It might be not writable in the Non-secure world if the AW bit in the SCR register is reset. For details of how to use the A bit see Imprecise Data Abort mask in the CPSR/SPSR on page 2-47.

2.10.7The control bits

The bottom eight bits of a PSR are known collectively as the control bits. They are the:

•Interrupt disable bits

•T bit

•Mode bits on page 2-28.

The control bits change when an exception occurs. When the processor is operating in a privileged mode, software can manipulate these bits.

Interrupt disable bits

The I and F bits are the interrupt disable bits:

•When the I bit is set, IRQ interrupts are disabled.

•When the F bit is set, FIQ interrupts are disabled. FIQ can be non-maskable in the Non-secure world if the FW bit in SCR register is reset

Note

You can change the SPSR F bit in the Non-secure world but this does not update the CPSR if the SCR bit 4 (FW) does not permit it.

T bit

The T bit reflects the operating state:

•when the T bit is set, the processor is executing in Thumb state

•when the T bit is clear, the processor is executing in ARM state, or Jazelle state depending on the J bit.

Note

Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If an MSR instruction does try to modify this bit the result is architecturally Unpredictable. In the ARM1176JZ-S processor this bit is not affected.