- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
B
Quick Reference
This appendix provides two methods of equating ac_shell commands to GUI menu commands. Table B-1 through Table B-12 are ordered according to the GUI menu in which the commands are presented. Table B-13 is an alphabetical list of ac_shell commands and the corresponding GUI menu command.
Table B-1 Main Menu – File and ac_shell Equivalents
GUI Option/ |
ac_shell Equivalent |
|
Command |
||
|
||
|
|
|
New |
do_remove_design -all |
|
Open |
read_adb |
|
|
read_alf |
|
|
read_verilog |
|
|
read_vhdl |
|
|
read_edif |
|
|
read_ctlf |
|
|
read_pdef (PKS only) |
|
|
source tcl_filename |
|
Save |
write_adb |
|
|
write_vhdl |
|
|
write_verilog |
|
|
write_pdef (PKS only) |
|
|
write_edif |
|
|
write_gcf_assertions |
|
Save |
|
|
Preferences |
none |
|
Save Console |
|
|
Log |
none |
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Table B-1 Main Menu – File and ac_shell Equivalents,continued
GUI Option/ |
ac_shell Equivalent |
|
Command |
||
|
||
|
|
|
Printer Setup |
none |
|
Exit |
none |
|
|
|
Table B-2 Main Menu – Edit and ac_shell Equivalents
GUI Option/ |
ac_shell Equivalent |
|
Command |
||
|
||
|
|
|
Cut |
none |
|
Copy |
none |
|
Paste |
none |
|
Clear |
clear (Unix command) |
|
User Command |
none |
|
|
|
Table B-3 Main Menu – View and ac_shell Equivalents
GUI Option/ |
ac_shell Equivalent |
|
Command |
||
|
||
|
|
|
Toolbar Hide |
none |
|
Refresh View |
none |
|
General |
|
|
Preferences |
none (including nested options) |
|
Schematic |
|
|
Preferences |
none (including nested options) |
|
Console |
|
|
Message Monitor |
none |
|
|
|
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Table B-4 Main Menu – Commands and ac_shell Equivalents
GUI Option/ |
ac_shell Equivalent |
|
Command |
||
|
||
|
|
|
Set Operating |
|
|
Parameters |
set_operating_parameters |
|
Set Target |
|
|
Technology |
set_global -target_technology |
|
Load DCL Rules |
load_dcl_rule |
|
Unload DCL |
|
|
Rules |
unload_dcl_rule |
|
Check Netlist |
check_netlist |
|
Check Timing |
check_timing |
|
Check Test Rules |
check_dft_rules |
|
Build Generic |
do_build_generic |
|
Optimize |
do_optimize |
|
|
|
Table B-5 Main Menu – Reports and ac_shell Equivalents
GUI Option/
ac_shell Equivalent
Command
Timing report_timing
Area report_area
Library report_library
Hierarchy report_hierarchy
Design Rules report_design_rule_violations
VHDL Library report_vhdl_libraries
End Point Slack
Histogram none
Path Histogram none
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The Main Menu – Window commands are accessed through icons on the editor and viewer tool bars. The table below lists only the GUI options/commands that have ac_shell equivalents.
Table B-6 Main Menu – Window and ac_shell Equivalents
GUI Option/
ac_shell Equivalent
Command
Save and Parse write_verilog and read_verilog write_vhdl and read_vhdl
Uniquify
Schematic
Instances do_uniquely_instantiate
Table B-7 Main Menu – Help and ac_shell Equivalents
GUI Option/
ac_shell Equivalent
Command
About Ambit ac_shell displays a startup banner when opening BuildGates
Schematic none
Symbol Utilities
Documentation none
The table below lists only the GUI module browser options/commands that have ac_shell equivalents.
Table B-8 Module Browser and ac_shell Equivalents
GUI Option/
ac_shell Equivalent
Command
Set Current set_current_module
Module
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Table B-8 Module Browser and ac_shell Equivalents, continued
GUI Option/
ac_shell Equivalent
Command
Set Top Timing set_top_timing_module
Module
Set Don’t Modify set_dont_modify
Reset Don’t
Modify reset_dont_modify
The table below lists the only GUI variable browser command that has an ac_shell equivalent.
Table B-9 Variable Browser and ac_shell Equivalent
GUI Command ac_shell Equivalent
set_global set_global
The table below lists the only HDL editor (within the work area tools area) command that has an ac_shell equivalent.
Table B-10 HDL Editor and ac_shell Equivalents
GUI Option/
ac_shell Equivalent
Command
Save and Parse write_verilog and read_verilog write_vhdl and read_vhdl
The table below lists the only Tcl editor (within the work area tools area) commandsthat has an ac_shell equivalent.
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Table B-11 Tcl Editor and ac_shell Equivalents
GUI Option/
ac_shell Equivalent
Command
Save and Parse save the Tcl file and
source tcl-filename
The table below lists the constraints tool (within the work area tools area) options/commands and the ac_shell equivalents.
Table B-12 Constraints Tool and ac_shell Equivalents
GUI Option/Command |
ac_shell Equivalent |
|
|
Ideal Clock Pop-Up Menu: |
|
Refresh Clock Table |
none |
New Ideal Clock |
set_clock |
Port Clock Pop-Up Menu: |
|
New Port Clock |
set_clock_root |
|
set_clock_insertion_delay |
|
set_clock_required_time |
Remove Clock Assertions |
remove_assertion |
Port Constraints Pop-Up Menu: |
|
Show Default Clock |
none |
Toggle Polarity |
set_clock_root |
|
set_clock_insertion_delay |
Create Positive Edge Clock |
set_clock_root |
|
set_clock_insertion_delay |
Create Negative Edge Clock |
set_clock_root |
|
set_clock_insertion_delay |
Report Port Assertion |
none |
Remove Port Assertion |
remove_assertion |
|
|
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Table B-13 ac_shell Commands and GUI Menu Equivalents
ac_shell Command |
GUI Menu Equivalent |
|
|
check_dft_rules |
Main Menu – Commands –Check Test Rules |
check_netlist |
Main Menu – Commands – Check Netlist |
check_timing |
Main Menu – Commands – Check Timing |
clear (Unix command) |
Main Menu – Edit – Clear |
do_build_generic |
Main Menu – Commands – Build Generic |
do_optimize |
Main Menu – Commands – Optimize |
do_remove_design -all |
Main Menu – File – Open |
do_uniquely_instantiate |
Schematic Editor – Uniquify Instances |
load_dcl_rule |
Main Menu – Commands – Load DCL Rules |
read_adb |
Main Menu – File – Open |
read_alf |
Main Menu – File – Open |
read_ctlf |
Main Menu – File – Open |
read_edif |
Main Menu – File – Open |
read_pdef (PKS only) |
Main Menu – File – Open |
read_verilog |
Main Menu – File – Open |
|
HDL Editor – Open HDL File |
read_vhdl |
Main Menu – File – Open |
|
HDL Editor – Open HDL File |
remove_assertion |
Constraints Tool – Remove Port Assertions |
report_area |
Main Menu – Reports – Area Report |
report_design_rule_ |
Main Menu – Reports – Design Rules Report |
violations |
|
report_hierarchy |
Main Menu – Reports – Hierarchy Report |
report_library |
Main Menu – Reports – Library Report |
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Table B-13 ac_shell Commands and GUI Menu Equivalents, continued
ac_shell Command |
GUI Menu Equivalent |
|
|
report_timing |
Main Menu – Reports – Timing Report |
report_vhdl_libraries |
Main Menu – Reports – VHDL Library Report |
reset_dont_modify |
Module Browser – Reset Don’t Modify |
set_clock |
Constraints Tool – New Ideal Clock |
set_clock_root |
Constraints Tool – New Port Clock ... |
set_clock_insertion_delay |
Constraints Tool – Toggle Polarity |
|
Constraints Tool – Create Positive Edge Clock |
|
Constraints Tool – Create Negative Edge Clock |
set_clock_required_time |
Constraints Tool – New Port Clock ... |
|
Constraints Tool – Toggle Polarity |
|
Constraints Tool – Create Positive Edge Clock |
|
Constraints Tool – Create Negative Edge Clock |
set_current_module |
Module Browser – Set Current Module |
set_dont_modify |
Module Browser – Set Don’t Modify |
set_global |
Varible Browser – set_global |
set_global target_ |
Main Menu – Commands – Set Target Technology |
technology |
|
set_operating_parameters |
Main Menu – Commands – Set Operating Parameters |
set_top_timing_module |
Module Browser – Set Top Timing Module |
source filename |
Main Menu – File – Open |
unload_dcl_rule |
Main Menu – Commands – Unload DCL Rules |
write_adb |
Main Menu – File – Save |
write_edif |
Main Menu – File – Save |
write_gcf_assertions |
Main Menu – File – Save |
write_pdef (PKS only) |
Main Menu – File – Save |
write_verilog |
Main Menu – File – Save |
|
HDL Editor – Save HDL File |
write_vhdl |
Main Menu – File – Save |
|
HDL Editor – Save HDL File |
|
|
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