- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
Report Generation
Finite State Machine Reports
The report for finite state machine (FSM) is generated using the following command:
report_fsm [-vector vector_name] [-state_table] [-encoding] [-hierarchical] [{> | >>} filename]
where:
■vector_name is the state vector name. If not specified, all FSMs in the current module
are reported
■filename is the name of the generated report file. If omitted, the report is displayed on the standard output.
The -state_table option extracts a state transition table in a report form. The -encoding option reports all state assignments for each selected FSM.
The -hierarchical option reports all FSMs in any module in the downward path of current module.
If none of the above options are specified, a summary report with the following information is printed:
■Design (module) name, state vector name, file name and line number it was found in RTL model
■Number of states in this FSM, initial state, equivalent states, unreachable states, terminal states, preserved states, and number of transitions (arcs)
■Number and name of inputs to this FSM, unused inputs and hold signal
■Number and name of outputs from this FSM
■Clock signal and edge (rising or falling) that controls transitions in this FSM
■Encoding used, encoding size, whether any unreachable states were removed or any states were merged
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Ambit BuildGates Synthesis User Guide
Report Generation
Sample FSM Report
Below is a sample FSM report generated from the following command.
report_fsm > BG4.0_fsm_rep.rpt
+--------------------------------------- |
|
|
+ |
| Report |
| |
report _ fsm |
| |
|---------------- |
+ |
---------------------- |
| |
| Options |
| |
|
| |
+---------------- |
+---------------------- |
|
+ |
| Date |
| |
20000728.072056 |
| |
| Tool |
| |
ac _ shell |
| |
| Release |
| |
v4.0 - eng |
| |
| Version |
| |
Jul 26 2000 08:19:39 | |
|
+---------------- |
+---------------------- |
|
+ |
| Current Module | |
fsm2 |
| |
|
+--------------------------------------- |
|
|
+ |
+---------------------------------------------------------- |
|
|
+ |
| |
Finite State Machine Report |
| |
|
|---------------------------------------------------------- |
|
|
| |
| Design |
|
| fsm2 |
| |
| State Vector |
|
| state_reg |
| |
| File |
|
| /ambit/regress/bg/fsm//fsm2.0347.v | |
|
| Line |
|
| 31 |
| |
+--------------------- |
|
+------------------------------------ |
+ |
| States |
|
| 4 |
| |
| Initial states |
|
| (Sinit) |
| |
| Equivalent states |
| (Sinit Sfirst0)(Ssecond1 Sthird1) |
| |
|
| Unreachable states |
| <None> |
| |
|
| Terminal states |
| <None> |
| |
|
| Preserved states |
| <None> |
| |
|
| Transitions |
|
| 10 |
| |
+--------------------- |
|
+------------------------------------ |
+ |
| Inputs |
|
| 2 |
| |
| Input names |
|
| (PI_188 i) |
| |
| Unused inputs |
|
| <None> |
| |
| Hold signal |
|
| <None> |
| |
+--------------------- |
|
+------------------------------------ |
+ |
| Outputs |
|
| 1 |
| |
| Output names |
|
| (e) |
| |
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Ambit BuildGates Synthesis User Guide |
||
|
|
Report Generation |
|
|
|
|
|
+--------------------- |
+ |
------------------------------------ |
+ |
| Clock |
| |
clk |
| |
| Sense |
| |
rising - edge |
| |
+--------------------- |
+------------------------------------ |
|
+ |
| Encoding |
| |
<None> |
| |
| Encoding bit length | |
3 |
| |
|
+---------------------------------------------------------- |
|
|
+ |
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