Добавил:
Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
dsd1-10 / dsd-07=Verilog / esug.pdf
Скачиваний:
94
Добавлен:
05.06.2015
Размер:
1.38 Mб
Скачать

Ambit BuildGates Synthesis User Guide

Setting Constraints

Wire Load Model Selection

Figure 6-19 provides a flow chart of the algorithm used for selecting a wire load model for a net.

Figure 6-19 Finding Wire Load Model W for a Net N

Net N

Find module modx that encloses net N

Find hierarchically lowest level module M enclosing modx with user specified wire load model W

Wireload mode = enclosed

No

Yes

use area of top module

use area of module modx

Lookup wire load model W from module

Wire Load Model W

September 2000

163

Product Version 4.0

Ambit BuildGates Synthesis User Guide

Setting Constraints

Figure 6-20 depicts the wireload for a net, where T is the current top module, A is an instance inside T, and M1 and M2 are two instances inside A. The net net1 is fully contained inside A, but not fully contained inside either M1 or M2.

Figure 6-20 Estimating the Wireload for a Net

T

A

M1 M2

net1

top

enclosed

The wire load for net1 is estimated as follows:

Identify the enclosing module for net1. In the figure above, module A is the enclosing module.

For A or its parent modules (modules in its upward hierarchical path), identify if wire load table is already set.

If set, use it as the wire load table.

If not set, check the global wire load mode (by default, this is top).

If the mode is enclosed, use the area of enclosing module A to identify the wire load table.

If the mode is top, use the area of top module T to identify the wire load table.

The area look-up table for the wire load model is in the technology file.

September 2000

164

Product Version 4.0

Соседние файлы в папке dsd-07=Verilog