- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
Flow Procedures
Optimize the Design
Optimization can be performed either with the do_optimize command or with individual do_xform_ transform commands. For a list of transforms and which do_xform_ commands are equivalent to the do_optimize command, refer to Optimizing with Logic Transforms on page 177. For information on optimization before and after place and route, refer to:
Optimizing Before Place and Route on page 165 and Optimizing After Place and Route on page 185.
The target technology library must be set with the set_global target_technology target_libs command prior to running the do_optimize or do_xform_ commands.
The following paragraphs list the GUI and command line steps to specify the target technology library and write the assertions. The set_global step is typically run prior to beginning synthesis when all global parameters are set for the whole design. Also, the write_assertions command is used to save the design assertions in a .tcl file and is an optional step.
Specify Target Technology Library and Write the Assertions — GUI Procedure
1.Select Commands – Set Target Technology.
The Set Technology form appears with a list of available libraries.
2.Select the target technology and click Ok.
3.Assertions must be written from the ac_shell console in the GUI; type write_assertions filename.tcl and press Return.
Specify Target Technology Library and Write the Assertions — Command Line Procedure
1. Type set_global -target_technology target_lib and press Return.
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2. Type write_assertions filename.tcl and press Return.
The following paragraphs list the GUI and command line steps to optimize your design.
Optimize Design — GUI Procedure
1.Select Commands – Optimize.
The Optimize form appears.
2. Select optimize options and click Ok.
Optimize Design Using do_optimize — Command Line Procedure
In the example syntax below, optimization is performed with a high effort level, in auto flatten mode, and with time budgeting performed. Refer to the Envisia and Ambit Synthesis Command Reference for the full list of do_optimize options.
Type do_optimize -effort high -flatten auto -time_budget and press
Return.
Optimize Design Using do_xform_ — Command Line Procedure
Below are the steps to optimize a design with the do_xform_ commands that are equivalent to running the do_optimize command with its default options. Running transforms allows you to customize the optimization process. For example, the do_xform_map command maps a design to a specific technology library; omitting this command leaves the netlist as a purely generic one. Also, using do_xform_ commands instead of the do_optimize
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command allows you to perform other commands during the optimization process, such as generating reports or saving the design in various formats.
1.To propagate constants at the logic levels (0 or 1) throughout the design and crossing hierarchical boundaries, type do_xform_propagate_constants and press Ok.
2.To remove redundancies from the netlist, type do_xform_remove_redundancy and press Ok.
3.To apply boolean and algebraic algorithms and technology-independent transforms to achieve logic optimization and logic structuring, type do_xform_structure and press
Ok.
Note: The do_xform_optimize_generic command runs the transforms: do_xform_propagate_constants,do_xform_remove_redundancy, and do_xform_structure.
4.To map the generic netlist to the target technology library specified in the set_global command and apply to all hierarchical levels of the design, type
do_xform_map -hier and press Ok.
5.Type do_xform_timing_correction and press Ok to execute the following commands.
do_xform_buffer — Insert buffers at the non-critical fanouts of the critical nets to reduce the load driven by the critical net and improve the effective timing on the critical path.
do_xform_clone — Divide a net into two nets by duplicating the instance driving the original net to improve timing on critical path.
do_xform_fix_design_rule_violations — Correct design rule violators.
do_xform_reclaim_area — Replace cells with smaller area cells that have the same functionality and removes unnecessary buffers or clones. Applies to any transforms that reduce area, without worsening the worst negative slack.
do_xform_resize — If the library contains a choice of cells with the same functionality but different drives, replaces a cell with an equivalent cell of different drive if the new cell contributes toward meeting the goal of the transform.
6.To restructure and remap the critical path to meet the timing constraints, type do_xform_restructure and press Ok.
Note: The do_xform_optimize_slack command runs the transforms: do_xform_timing_correction and do_xform_restructure.
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Generate Reports
BuildGates synthesis provides the following report categories.
■Timing
■Area
■Library
■Hierarchy
■Design Rules
■VHDL Library
■End Point Histogram
■Path Histogram
Each of these categories has options which allow the customization of the report. For details on options and syntax, refer to the report_ commands in the Envisia and Ambit Synthesis Command Reference. For report strategies and additional examples, refer to Report Generation on page 191 of this book.
Below is an example of generating a timing report; the procedure for other reports is similar. Reports are saved in ascii format and can be viewed with an ascii editor.
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Generate Report — GUI Procedure
1.Select Reports – Timing.
The Report Timing form appears; the options part of the form is shown below.
2.Click the options and type the information that specifies the desired timing report and click the Generate Report icon on the Report Timing options form. The report is displayed in the text window to the left of the options form.
3.To save the report to a file, click on the Write Report to a File icon on the Report Timing options form and specify a file name and path.
Generate Report — Command Line Procedure
In the example syntax below, options are specified to display the worst late path to each violating endpoint that has a slack less than -1.0 and to write the report to a file named cpu_rep1.rpt.
To generate a timing report, type:
report_timing -max_slack -1.0 > cpu_rep1.rpt and press Return.
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