Ambit BuildGates Synthesis User Guide

Setting Constraints

set_current_module mycounter

For example purposes throughout this chapter, assume the module mycounter has four ports: ck, din, dout, and cntrl; constraints are applied to these ports.To apply constraints to ports of another module, the context (module) must be changed using the set_current_module command.

If a module has multiple instances in the design, and each instance requires different constraints to be applied to its design objects, a unique module must be generated for each instance. See the do_uniquely_instantiate command in the Envisia and Ambit Synthesis Command Reference.

Units in Constraints

The values used in constraints represent many different quantities. Cadence synthesis tools are “unitless” tools in the sense that when the quantities, whether constant or variable, are specified in consistent units, there is no need to explicitly mention units.

The data in the technology library is stored in appropriate units for delay, load, drive, capacitance, etc. All data you supply must be consistent with these units for the corresponding quantities.

Timing Constraints

Timing constraints guide Cadence synthesis software to achieve specified performance in the resulting netlist. Performance generally refers to the maximum clock frequency at which the design implementation (netlist) can operate and the critical paths in the design.

Timing Analysis

Timing constraints can be thought of as timing specifications placed on certain module ports. The timing specification on an input port is referred to as signal arrival time; the timing specification on an output port is referred to as signal required time. All timing constraints are associated with an ideal clock.

Timing analysis is an integral part of logic synthesis and is performed to ensure that all timing specifications are met. Cells are selected from technology libraries based on their functional, timing, and technology characteristics to achieve the goals set up by constraints. The timing analyzer is built-in as part of the synthesis program and guides the cell selection process to satisfy all the timing requirements.

Ambit BuildGates Synthesis User Guide

Setting Constraints

Setting up Timing Context

Timing context is specified by identifying the top timing module of the design hierarchy.

Subsequent commands that assert constraints or perform analysis refer to this timing module.

The set_top_timing_module command provides context for all timing constraints; the sample syntax is as follows:

set_top_timing_module module_name

where:

■module_name is the name of the module being set as the timing context.

The timing analyzer maintains the analysis and constraints pertaining to different timing contexts. Thus, the set_top_timing_module command can be viewed as a selection mechanism for timing contexts.

Ideal Clock Definition

An ideal clock must be defined as a global reference signal for all the data signals in the design. The command for defining an ideal clock is the set_clock command; the sample syntax for is as follows:

set_clock clock_name -period period -waveform {lead trail}

where:

■clock_name is the name used for the ideal clock.

■period is the period of the clock.

■lead is the time at which first transition on the clock occurs.

■trail is the time at which second transition on the clock occurs (period, lead, and trail are integer or real constants).

For example:

set_clock master -period 10 -waveform {0 5}

set_clock idealX -period 100 -waveform {30 90}

The first command defines an ideal clock called master with a period of 10, leading transition at 0, and trailing transition at 5. The second command defines an ideal clock called idealX with a period of 100, leading transition at 30, and trailing transition at 90.

Ambit BuildGates Synthesis User Guide

Setting Constraints

The leading transition does not imply a rising edge, nor does trailing transition imply a falling edge on the clock signal. The leading transition only indicates first transition, which may be a rising edge or a falling edge transition. The trailing transition is the opposite transition to the leading transition.

Figure 6-1 shows that an ideal clock definition can be treated either as a positive clock (leading transition is a rising edge transition) or as a negative clock (leading transition is a falling edge transition). The polarity of the clock gets defined when an input port is associated with the ideal clock as a clock port; see set_clock_insertion_delay command definition in Clock Insertion Delay Time.

Figure 6-1 Defining Ideal, Positive, and Negative Clocks

lead trail period

positive clock

negative clock

positive clock

negative clock

Each data signal arriving at a port is considered to be associated with either a leading or a trailing edge of the clock. That is, the signal change is associated with (was caused by) the leading or the trailing edge of the ideal clock. For example, the signal change in the output port of a flip-flop is caused by one of the following four events, as shown in Figure 6-2.

■A rising-edge triggered flip-flop causes a change at its output using a positive clock as shown in (a). In this case, the signal change is associated with the leading edge of the ideal clock.

Ambit BuildGates Synthesis User Guide

Setting Constraints

■A falling-edge triggered flip-flop causes a change at its output using a negative clock as shown in (b). In this case, the signal change is associated with the leading edge of the ideal clock - same as (a).

■A rising-edge triggered flip-flop causes a change at its output using a negative clock as shown in (c). In this case, the signal change is associated with the trailing edge of the ideal clock.

■A falling-edge triggered flip-flop causes a change at its output using a positive clock as shown in (d). In this case, the signal change is associated with the trailing edge of the ideal clock - same as (c)

Figure 6-2 Positive and Negative Clocks Controlling a Flip-Flop

In a single clock design, only one set_clock command is used. In a multi-phase clock system several set_clock commands are used to define each phase of the clock.

For a purely combinational design, an ideal clock (or any clock) definition is not necessary.

Clock Insertion Delay Time

Once ideal clocks are defined, the actual clock signals arriving at the input port of the design can be defined. The association between the ideal clock and the clock signal arriving at a

Ambit BuildGates Synthesis User Guide

Setting Constraints

clock port (for both clock insertion delay in the ideal and propagated modes) is made using the set_clock_insertion_delay command.

The command has two forms. The first one specifies clock insertion delay for an ideal clock waveform; the sample syntax is as follows:

set_clock_insertion_delay [-source] [-early] [-late] [-pvt {min, typ, max}]

[-rise] [-fall] [-clock clock] -pin pinlist insertion_delay

The second form is used for specifying clock insertion delay on a clock pin; the syntax is as follows:

set_clock_insertion_delay [-source] [-early | -late] [-pvt {min, typ, max}]

([-lead | -trail] list_of_clocks)} |

{([-rise | -fall] [-clock clock_name]} -pin list_of_pins) insertion_delay

where:

■list_of_clocks is the list of ideal clocks associated with the delay.

■insertion_delay is the time at the specified, rise, fall, lead, or trail.

■list_of_pi is the list of pins associated with the delay.

Figure 6-3 shows the timing relationship between the ideal clock (master) and the clock signal (ck).

Figure 6-3 Associating a Positive Clock Signal to an Ideal Clock

0.10.2 0.1

Figure 6-4 associates two clock ports c1 and c2 with the ideal clock A (as defined earlier) which has its rising edge at 91 and its falling edge at 32.