Ambit BuildGates Synthesis User Guide

6

Setting Constraints

The logic synthesis process requires two user inputs: a functional (RTL) model of the design and a set of constraints on the design. The constraints are divided into two groups: timing constraints and physical constraints. There are no user-specified constraints for design area because a design with smaller area (gate count) is always preferred over a design with larger area, when all other characteristics (e.g. timing) are the same. Cadence synthesis tools always strive for the smallest possible design area given timing and physical constraints.

The purpose of this chapter is to familiarize you with the process of setting constraints, consequently, only a subset of all of the possible constraints are provided in the way of example. The constraint examples in this chapter are presented in command line input format; GUI instructions are not provided. In addition, the example syntax may not include all possible options; the syntax is for example only.

For complete descriptions of all commands and their options, please refer to the Envisia and Ambit Synthesis Command Reference. For complete information on the methodology of setting constraints, refer to Setting Timing Constraints in the Envisia Timing Analysis User Guide.

Setting a Hierarchical Context

Constraints are placed on various design objects such as ports, nets, etc. In order to uniquely identify the design object used in the command, a module must be identified to provide a context where the design objects can be found. That is, design objects are searched for in a given module context.

The sample syntax for set_current_module is as follows.

set_current_module module_name

where:

■module_name is the name of the module that is being used as the current context.

For example, where mycounter is an example of a module design object: