Ambit BuildGates Synthesis User Guide

Optimizing After Place and Route

Both worst case and best case SDF timing are stored in the above example, although only a worst case timing library is loaded.

Reading SDF Data

The delay data extracted from a physical tool such as a floorplanner or a router can be imported using the Standard Delay Format (SDF) file. The syntax of the command is as follows:

read_sdf filename

where:

■filename is the name of the SDF file.

The design name in the SDF file must match the name of the current module. The timing data from SDF file is applied to the current module and its hierarchy. Both the cell delay data and the interconnect delay data are backannotated in the netlist. The minimum, typical and maximum delays are used from the SDF file. The backannotated delays overwrite the delays in the netlist database.

The name matching (of ports, nets, cells, and instances) between the SDF file and the netlist database is case sensitive.

Optimizing to Correct Late and Early Slack

Before optimization begins, each modules in the design should have only a single instance referring to it. If a module is instantiated more than once, modification will not be made to the module.

To automatically create copies of modules used more than once in the design and to bind instances to unique modules, use the following command:

do_uniquely_instantiate -hierarchical

Ambit BuildGates Synthesis User Guide

Optimizing After Place and Route

As shown in Figure 9-1, chip hierarchy is often organized with various JTAG modules, I/O cells, and a synthesizable core at the highest level.

Figure 9-1 Common Chip Hierarchy

Chip

The synthesizable core contains the majority of the chip logic. The other peripheral modules and cells at the top level are often manually instantiated. With this hierarchy structure, the preferred optimization strategy is to use the worst case timing from the constraints applied at the chip level, but perform all optimization work within the synthesizable core. This is accomplished by setting the top timing module at the chip level and setting the current module to core before invoking the optimization transform.

set_current_module core

set_top_timing_module chip

To optimize the timing of the design by using cell resizing and buffer insertion, use the following transform command:

do_xform_timing_correction -dont_reclaim_area -resize -buffer

Note: For all transforms except do_xform_optimize_slack, only the - dont_reclaim_area option disables all reclaim area. For do_xform_optimize_slack, the reclaim area in the final timing correction phase is disabled.

Area reclamation is disabled to prevent removing buffers and their corresponding annotated nets.

If timing violations are still present after optimization, it is helpful to categorize the types of timing failures. To report up to 1000 failing timing paths in a design, use the following command:

report_timing -net -max_points 1000 -max_slack 0

Ambit BuildGates Synthesis User Guide

Optimizing After Place and Route

After determining the root cause for the failures, it may be necessary to change the physical placement of the components to reduce critical path capacitance. More aggressive synthesis transforms, such as do_xform_optimize_slack, can also be used to restructure failing paths, although annotated timing and parasitic information will be discarded for restructured components.

To restructure failing paths (and discard annotated timing and parasitic information for restructured components), use the following command:

do_xform_optimize_slack

Area reclamation with parasitic backannotation is recommended only through resize operations and can be performed with the following command before or after fixing late slack:

do_xform_reclaim_area -resize

Early or hold time violators are corrected next. For a full explanation of this process refer to the Envisia Timing Analysis User Guide, Finding and Fixing Violations chapter.