Ambit BuildGates Synthesis User Guide

Setting Constraints

Table 6-3 Float Value Stored at From and To Pin (After Third Command)

x indicates no change due to this command

Setting Drive Cell for Input Ports

To accurately model the drive capability of an external driver connected to the input port, identify the library cell that drives the input port of your design. This procedure helps decide how many loads can be driven directly from the input port without creating too large a load (and therefore an increased slew time). If the library cell (driver) has multiple output ports, then the output port connection must be identified.

You will know the driver cell information under the following conditions: if the upstream block was already synthesized or if a decision was already made to use certain drivers due to various circuit-related design issues (see Figure 6-12).

Ambit BuildGates Synthesis User Guide

Setting Constraints

Figure 6-12 Selecting a Driver for Input Port

The set_drive_cell command is used to specify the library cells and has the following syntax:

set_drive_cell [-early | -late][-library library_name] [-library_rise library_name][-library_fall library_name] [-cell cell_name] [-cell_rise cell_name] [-cell_fall cell_name] [-pin pin_name] [-pin_rise pin_name] [-pin_fall pin_name] [-from_pin from_pin_name] [-from_pin_rise from_pin_name]

[-from_pin_fall from_pin_name] [-rise_source_edge R|F]

[-fall_source_edge R|F] [-clock clock_name]

[-lead | -trail | -pos | -neg] [-source_slew slew_value]

where:

■cell_name is the name of the driver cell.

■library_name is the library name of the driver cell.

■pin_name is the name of the output pin (port) of the driver cell.

■from_pin_name is the name of the input pin (port) that has an arc to the output pin.

■port_list is the list of ports driven by the driver.

■clock_name is the name of the ideal clock controlling the signal.

■slew_value is the slew value for the signal at the input of the drive cell.

The late or early options specify whether the driver provides an early or late signal arrival at the input port of your design. If it is not specified, the driver is considered in both early and late timing analysis.

Ambit BuildGates Synthesis User Guide

Setting Constraints

The cell options specify whether the driver specified by the cellname is providing a rising transition driver (-cell_rise cellname), a falling transition driver (-cell_fall cellname), or both (-cell cellname). Thus, it is possible to distinguish the cells that provide drivers for specific transitions. One of the three (-cell, -cell_rise, -cell_fall) options must be specified.

The library options specify the name of the library which contains the driver cell. If one driver cell is causing both the rising and falling edge transitions at the input port, or different driver cells are causing the transitions but they both belong to the same library, only the -library option is needed. If the driver cells causing the rising and falling edge transitions at the input port belong to different libraries, -library_rise and -library_fall options must be used to identify the specific libraries. If only one library is used in the design, the library name need not be specified.

The pin options specify the output port of the driver cell that drives the signal at the input port of your design. This option is required if the driver cell has multiple output ports. If the output pin (port) of the driver cell causes both the rising and falling edge transitions at the input port, the -pin option should be used to identify the output port of the driver cell. If a port of the driver cell is causing only a rising edge or falling edge transition, -pin_rise or -pin_fall, respectively, should be used to identify the port name.

The from_pin option specifies the input port of the driver cell that has a controlling timing arc to the output port of the driver cell which is connected to the input port of the design. This option is required if there are multiple timing arcs in the driver cell from its input ports to its output port(s). As with the other options, -from_pin_rise and -from_pin_fall options can be used to distinguish the controlling timing arc that causes a rising edge or a falling a edge transition at the input port.

The -rise_source_edge option specifies whether the rising edge (R) or falling edge (F) at the frompin is controlling the rising edge transition at the input port of the design. The -fall_source_edge option specifies whether the rising edge (R) or falling edge(F) at the from_pin is controlling the falling edge transition at the input port of the design.

The late or early options specify the pertinent edge of the ideal clock with which the signal required time is specified.

Setting Drive Resistance

The command set_drive_resistance, a simpler form of the set_drive_cell command, can be used in many situations where the drive resistance can be specified. The arrival time at the input port is modified by adding the RC factor to the specified arrival time at the input port. The RC constant is the capacitance as seen at the input port multiplied by the drive resistance.

Ambit BuildGates Synthesis User Guide

Setting Constraints

The syntax for the set_drive_resistance command is as follows:

set_drive_resistance -clock clock_name [-rise | -fall]

[-early | -late] {-lead | -trail} [-slew_res slew_res_value]

[-slew_intrinsic slew_intrinsic_value] value port_list

where:

■clock_name is the name of the ideal clock.

■slew_resistance_value is value of resistance used in the slew computation.

■slew_resistance_value is intrinsic value of slew used in the slew computation.

■value is the resistance value.

■port_list is the list of input ports for which drive resistance is specified.

The rise or fall options indicate whether the drive resistance is applicable to only the rising edge or falling edge transition at the input port. If this option is not specified than the drive resistance is applied to both transitions at the input port.

The early or late options indicate whether the drive resistance should be applied to the early arrival time or the late arrival time for timing analysis.

The late or early options specify the pertinent edge of the ideal clock with which the signal required time is specified.

Slew Related Commands

Slew is a measure of the slope of an arriving signal. For a signal changing from low (high) to high (low), slew time is represented by the time it takes to reach from low (high) level to high (low) level. It is a common practice to consider the change between two predefined thresholds around the two levels, e.g. 20% and 80%. See Figure 6-13 for a graphical representation of slew.

Ambit BuildGates Synthesis User Guide

Setting Constraints

Figure 6-13 Rising and Falling Edges of a Signal

Slew is the slope of the signal from 20% of target level to 80%

Two commands are related to slew: set_slew_time_limit and set_slew_propagation_mode and are defined in the following paragraphs.

Setting Slew Limit

Design rules of a process require that slew time at each input and output port be less than a predefined limit. The set_slew_time_limit command syntax is as follows:

set_slew_time_limit float port_list

where:

■float is the maximum slew allowed.

■port_list is the list of ports to which the limit applies.

For example,

set_slew_time_limit 2.3 {bus1 bus2}

The float for bus1 and bus2 is set at 2.3, i.e. the slew at which the signal at bus1 or bus2 cannot exceed. The float is usually derived from the design rule constraints placed on the cells that the output port is driving or the input port by which it is driven.

Setting Slew Propagation Mode

Three methods of accurate slew propagation are available in BuildGates synthesis:

■Worst

■Critical

■Fast (default)

Ambit BuildGates Synthesis User Guide

Setting Constraints

Both modes propagate output slew through all logic levels and are specified using the global variable.

The worst slew propagation mode is set using the following arguments within the set_global command.

set_global slew_propagation_mode {worst_slew | crit_slew | fast}

Fast Slew

Fast slew propagation mode calculates the output slews independent of the input slews. The output slews are based only on the drive strength of the cell in question and on the loading conditions on the output pin. This mode has the fastest runtime, but is the least accurate in terms of results. Figure 6-14 provides an example of fast slew propagation.

Figure 6-14 Fast Slew Propagation Mode

(delay, slew)

Worst Slew

Using worst slew propagation mode, the effect of the input slew on the output slew for all arcs is calculated and the worst slew effect is combined into the output slew along with the effect of output loading. Consequently, if the worst slew effect is associated with an input that arrived much earlier than the other inputs, that slew effect is still used.

The worst slew algorithm is more pessimistic than the critical slew propagation mode described below.

Figure 6-15 provides an example of worst slew propagation. Even though the arrival time at input a is earlier than at b, the input slew for a is so much greater that the effect on the output slew from input a is likely worse than the effect from input b. Thus the effect from a will be used.

Ambit BuildGates Synthesis User Guide

Setting Constraints

Figure 6-15 Worst Slew Propagation Mode

Critical Slew

In critical slew propagation mode, the effect of the critical input slew from the latest arriving signal and the effect of output loading is used to calculate the total output slew. Figure 6-16 shows that the effect of the input slew from the latest arriving signal, (2, 2), is used in the output slew calculation.

Figure 6-16 Critical Slew Propagation Mode

(arrival time, slew)