- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
Report Generation
Fanin and Fanout Reports
The fanin and fanout reports are generated using the following commands:
report_fanin [-level integer] [-tristate] [-sequential] [-hierarchical] [{> | >>} filename] [-maxline integer] list_of_pin_path_or_id
report_fanout [-level integer] [-tristate] [-sequential] [-hierarchical] [{> | >>} filename] [-maxline integer] list_of_pin_path_or_id
where:
■filename is the name of the generated report file. If filename is given, the report is written to the file. If the filename is omitted, the report is displayed on the standard output.
■list_of_pin_path_or_id is the Tcl list of pin or port path names or object identifiers for which to start the fanin or fanout cone search.
The -hierarchical option allows the command to traverse backwards across hierarchy boundaries to generate a report. By default for fanin, it will stop at the input port and it will report on the fanin path starting from that port (treated as the start point). By default for fanout, it will stop at output ports and report the fanout path ending to that port (treated as the end point).
The -level option specifies the number of levels which need to be traversed for generating the report.
The -maxline option TBD.
The -tristate option includes the tristates in the path.
The -sequential option includes the sequential cells in the path. By default the reporting stops at the encounter of the first sequential cell in the path.
September 2000 |
203 |
Product Version 4.0 |
Ambit BuildGates Synthesis User Guide
Report Generation
Sample Fanin Report
Below is a sample fanin report generated from the following command. The fanout report is similar and is not shown.
report_fanin -level 3 -hierarchical address > BG4.0_fanin_rep.rpt
+----------------------------------------- |
|
|
+ |
| Report |
| |
report _ fanin |
| |
|--------- |
+ |
------------------------------- |
| |
| Options | |
- level 3 - hierarchial address | |
||
+--------- |
+------------------------------- |
|
+ |
| Date |
| |
20000728.075258 |
| |
| Tool |
| |
ac _ shell |
| |
| Release | |
v4.0 - eng |
| |
|
| Version | |
Jul 27 2000 13:27:20 |
| |
|
+--------- |
+------------------------------- |
|
+ |
| Module |
| |
cpu |
| |
+----------------------------------------- |
|
|
+ |
+ |
------------------------------------------------------------ |
|
|
|
+ |
| Level |
| From(Instance/Pin) |
| To(Instance/Pin) |
| Net |
| |
|
|------- -------------------- ------------------ ------------ |
|
+ |
+ |
+ |
| |
| |
1 |
| ireg1/r[5] |
| i_8/A |
| iraddr[4] |
| |
| |
2 |
| i_8/Z |
| address[4] |
| address[4] | |
|
+------- -------------------- ------------------ ------------ |
|
+ |
+ |
+ |
+ |
| |
1 |
| pcount1/q[5] |
| i_8/B |
| pcout[4] |
| |
| |
2 |
| i_8/Z |
| address[4] |
| address[4] | |
|
+------- -------------------- ------------------ ------------ |
|
+ |
+ |
+ |
+ |
| |
1 |
| decode1/sel_adr |
| i_8/S |
| n_670 |
| |
| |
2 |
| i_8/Z |
| address[4] |
| address[4] | |
|
+------- -------------------- ------------------ ------------ |
|
+ |
+ |
+ |
+ |
| |
1 |
| ireg1/r[4] |
| i_9/A |
| iraddr[3] |
| |
| |
2 |
| i_9/Z |
| address[3] |
| address[3] | |
|
+------- -------------------- ------------------ ------------ |
|
+ |
+ |
+ |
+ |
| |
1 |
| pcount1/q[4] |
| i_9/B |
| pcout[3] |
| |
| |
2 |
| i_9/Z |
| address[3] |
| address[3] | |
|
+------- -------------------- ------------------ ------------ |
|
+ |
+ |
+ |
+ |
| |
1 |
| decode1/sel_adr |
| i_9/S |
| n_670 |
| |
| |
2 |
| i_9/Z |
| address[3] |
| address[3] | |
|
+------- -------------------- ------------------ ------------ |
|
+ |
+ |
+ |
+ |
| |
1 |
| ireg1/r[3] |
| i_10/A |
| iraddr[2] |
| |
| |
2 |
| i_10/Z |
| address[2] |
| address[2] | |
September 2000 |
204 |
Product Version 4.0 |
|
|
Ambit BuildGates Synthesis User Guide |
|||
|
|
|
Report Generation |
|
|
|
|
|
|
|
|
+ |
------- |
+-------------------- |
+------------------ |
+------------ |
+ |
| |
1 |
| pcount1/q[3] |
| i_10/B |
| pcout[2] |
| |
| |
2 |
| i_10/Z |
| address[2] |
| address[2] | |
|
+------- |
|
+-------------------- |
+------------------ |
+------------ |
+ |
| |
1 |
| decode1/sel_adr |
| i_10/S |
| n_670 |
| |
| |
2 |
| i_10/Z |
| address[2] |
| address[2] | |
|
+------- |
|
+-------------------- |
+------------------ |
+------------ |
+ |
| |
1 |
| ireg1/r[2] |
| i_11/A |
| iraddr[1] |
| |
| |
2 |
| i_11/Z |
| address[1] |
| address[1] | |
|
+------- |
|
+-------------------- |
+------------------ |
+------------ |
+ |
| |
1 |
| pcount1/q[2] |
| i_11/B |
| pcout[1] |
| |
| |
2 |
| i_11/Z |
| address[1] |
| address[1] | |
|
+------- |
|
+-------------------- |
+------------------ |
+------------ |
+ |
| |
1 |
| decode1/sel_adr |
| i_11/S |
| n_670 |
| |
| |
2 |
| i_11/Z |
| address[1] |
| address[1] | |
|
+------- |
|
+-------------------- |
+------------------ |
+------------ |
+ |
| |
1 |
| ireg1/r[1] |
| i_12/A |
| iraddr[0] |
| |
| |
2 |
| i_12/Z |
| address[0] |
| address[0] | |
|
+------- |
|
+-------------------- |
+------------------ |
+------------ |
+ |
| |
1 |
| pcount1/q[1] |
| i_12/B |
| pcout[0] |
| |
| |
2 |
| i_12/Z |
| address[0] |
| address[0] | |
|
+------- |
|
+-------------------- |
+------------------ |
+------------ |
+ |
| |
1 |
| decode1/sel_adr |
| i_12/S |
| n_670 |
| |
| |
2 |
| i_12/Z |
| address[0] |
| address[0] | |
|
+------------------------------------------------------------ |
|
|
|
|
+ |
September 2000 |
205 |
Product Version 4.0 |