dsd1-10 / dsd-07=Verilog / digital
.doc(GCF
(HEADER
(VERSION "GCF Version 1.4" )
(DESIGN "digital" )
(DATE "Friday, February 25, 2005 - 10:05:47" )
(PROGRAM "BuildGates" "v5.13-s022" "Cadence Design Systems, Inc." )
(DELIMITERS "/[]" )
(TIME_SCALE 1E-9 )
(CAP_SCALE 1E-12 )
(RES_SCALE 1E3 )
(VOLTAGE_SCALE 1E0 )
(POWER_SCALE 1E-9 )
)
(GLOBALS
(GLOBALS_SUBSET ENVIRONMENT
(PROCESS 1.0000 1.0000)
(VOLTAGE 3.0000 3.0000)
(TEMPERATURE 25.0000 25.0000)
(OPERATING_CONDITIONS "typical" 1.0000 3.0000 25.0000)
(EXTENSION "SCALE_TO" LIBRARY_THRESHOLDS) (EXTENSION "DELAY_ALGORITHM" DARTU_PILEGGI) (VOLTAGE_THRESHOLD 10.0000 90.0000)
(EXTENSION "CTLF_FILES"
(
/net/sungate/export/home/sasha/GSCLib_2.0/timing/GSCLib_2.0_prelim3.tlf
)
)
)
)
(CELL ()
(SUBSET TIMING
(ENVIRONMENT
(INPUT_SLEW 0.0000 0.0000 0.0000 0.0000)
(LEVEL 1 (INTERNAL_SLEW 0.0000 0.0000 0.0000 0.0000) )
)
(EXCEPTIONS
(LEVEL 1 (CLOCK_MODE IDEAL) )
)
)
)
)