Добавил:
Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.
Вуз: Предмет: Файл:
dsd1-10 / dsd-07=Verilog / esug.pdf
Скачиваний:
94
Добавлен:
05.06.2015
Размер:
1.38 Mб
Скачать

Ambit BuildGates Synthesis User Guide

8

Optimizing with Logic Transforms

This chapter provides a basic understanding of the logic optimization transforms. It assumes a basic knowledge of programming Tcl and familiarity with the logic optimization process.

The purpose of this chapter is to familiarize you with the transformation commands used in optimization, consequently, only a subset of the possible transforms are provided in the way of example. The examples in this chapter are presented in command line input format and may not include all possible options; the syntax is for example only. For complete descriptions of all commands and their options, please refer to the Envisia and Ambit Synthesis Command Reference.

Introduction to Transforms

A transform is a command that changes or transforms the structure of the logic in the current design. During optimization, transforms are used repeatedly to reach design goals. Transforms examine the current logic implementation and perform changes that improve the logic implementation according to a global cost function set by various constraints.

A fundamental advantage of the Ambit® BuildGates® synthesis software is the ability to call transforms individually during logic optimization. For example, if a designer has taken time to structure logic at the RTL level, it is simple to avoid the “structuring” step of logic optimization by omitting that step in the flow. In other situations it may be advantageous to perform bufferinsertion only without modifying the cell selection of a netlist.

The transformations are performed only if the resulting netlist continues to meet all of the timing constraints previously met and if the change to the netlist allows the design to meet additional constraints. The transforms do not modify logic if the quality of the netlist is not improved.

Below is a list of BuildGates synthesis transforms:

do_dissolve_hierarchy

do_optimize

do_xform_buffer

September 2000

177

Product Version 4.0

Соседние файлы в папке dsd-07=Verilog