Ambit BuildGates Synthesis User Guide

Optimizing After Place and Route

Other fields can be added to the format as desired. Unexpected large capacitances may be annotated to nets. When this happens, it’s helpful to analyze whether the capacitance can be defrayed by reducing the fanout and how much timing improvement can be made by correcting slew rates.

To enhance timing analysis using report_timing, it is recommended that the -net switch be used to separate the wire RC delay from the cell I/O delay. Wire delays are noted on a cell’s input pins and cell I/O delays are noted on a cell’s output pins.

Backannotating

After place and route of the design, extraction tools calculate the capacitance and resistance information for individual nets. This net RC information may be used by a delay calculator (external to the BuildGates synthesis tool) to create a new timing view of the design. Timing information is conventionally stored in a Standard Delay Format (SDF) file. Individual net RC and design SDF timing information is annotated to the design within the BuildGates synthesis software to provide an accurate timing and design rule violation view of the design.

It may seem redundant to annotate both RC and SDF timing information, but both annotation types are needed. Timing arcs and cell timing checks annotated with SDF override the delay calculator within the software for the same parameters. Some SDF generators do not annotate all necessary arcs and timing checks, in which case the net RCs are useful for proper delay calculation. Also, SDF annotation does not cover important design rule considerations such as signal slew (or ramp) times and capacitance information. Furthermore, the BuildGates synthesis software accepts only lumped net RC information. Delay calculators that use distributed RC information can calculate unique wire delays for each receiver on a common net and store the parameters with SDF INTERCONNECT statements.

A Script Showing the Backannotation of a Design

The following example script shows the reading and backannotation of a design.

# Read timing libraries

set TargetTech [read_alf stdcell_wccom.alf] set_global target_technology $TargetTech set_operating_conditions WORST_CASE

# load design read_verilog chip.v do_build_generic

Ambit BuildGates Synthesis User Guide

Optimizing After Place and Route

set_top_timing_module chip set_current_module chip

#Set up timing constraints on the design source TimingConstraints.tcl

#Annotate Capacitance Information source WireLoadAnnotation.tcl

#Annotate Resistance Information

source WireResistanceAnnotation.tcl

#Annotate SDF information - Worst Case Timing read_sdf chip_wc.SDF

#Annotate SDF information - Best Case Timing read_sdf -min -store_as_min chip_bc.SDF

The list below provides file descriptions for the above example:

■TimingConstraints.tcl

Contains timing information to set clocks, data arrival and required times, and timing exceptions, such as false and multicycle paths on the design. The TimingConstraints.tcl file is also useful for annotating wire-load models for the design.

■WireLoadAnnotation.tcl

Contains wire capacitance settings for every interconnect in the design. The following syntax is used for annotating wire capacitance:

set_wire_capacitance capacitance_value path_to_net

■WireResistanceAnnotation.tcl

Contains wire resistance settings for every interconnect in the design. The following syntax is used for annotating wire resistance:

set_wire_resistance resistance_value path_to_net

■set_operating_conditions WORST_CASE

Loads the worst case timing library.

■read_sdf -max -store_as_max chip_wc.SDF

Stores the worst case timing information.

■read_sdf -min -store_as_min chip_bc.SDF

Stores the best case timing information.