Ambit BuildGates Synthesis User Guide

4

Flow Procedures

This chapter provides a high-level tutorial of the tasks of a typical synthesis flow. The tasks are presented in terms of both the command line instructions and the GUI procedures.

Refer to Key Bindings and Mouse Operations on page 31 for assistance in navigating the GUI editors and ac_shell console, and Syntax Conventions on page 10 in the Preface for command line syntax.

Typical Synthesis Flow

The typical high-level flow in BuildGates synthesis is shown in Figure 4-1 and consists of the following tasks.

■Read Libraries

■Read Design Data

■Build Generic Design

■Set Timing Constraints

■Optimize Design

■Generate Reports

■Save Final Netlist

The actual order of these tasks can vary and overlap. For example, you may want to generate reports both before and after optimizing the design. The following sections will expand and explain each of the tasks in the flow.

Ambit BuildGates Synthesis User Guide

Flow Procedures

Figure 4-1 Typical Synthesis Flow

Chip Planning

Read Libraries

Read Design Data

Build Generic Design

Set Timing Constraints

Optimize Design

Generate Reports

Save Final Netlist

Synthesis Complete

Ambit BuildGates Synthesis User Guide

Flow Procedures

Read the Libraries

Typically when running the Ambit BuildGates synthesis software, the first step is to load the timing and power libraries needed in the chip design. Cadence supports the following libraries.

■Ambit Library Format — ALF

■Cadence Timing Library Format 4.1 — TLF4.1

■IEEE 1481 Delay Calculation Language — DCL (a form of Delay and Power Calculation

System — DCPS)

■Open Library API — OLA v1.0.2

■Synopsys .lib format

■Graybox modeling

The BuildGates synthesis software accepts library file input in .alf and .ctlf formats.This section provides an overview of the libraries; libraries are explained in detail in the Envisia Timing Analysis User Guide, Using Timing Libraries chapter.

The DCL compiler, ndcl, compiles DCL into a binary Delay and Power Calculation Module (DPCM). The DPCM is an executable shared library that is linked to the BuildGates synthesis database at runtime. The DCL compiler is available through Cadence for library development purposes.

To use DCL libraries, a .alf library is loaded using the read_alf command, then a DCL library (or more accurately a DPCM) is loaded with the load_dcl_rule command followed by a read_library_update command. When the DPCM library is loaded after an .alf, all timing information is derived from the DPCM specified by the read_library_update file, and all cell function is derived from the .alf. If the DPCM contains cell properties (like area) and pin properties (like capacitance and wireloads), the DPCM takes precedence over the

.alf and will override any similar information provided by the .alf. If the DPCM does not contain this information, the cell and pin properties and wireloads from the .alf will be used. To map to multiple libraries, one library is loaded using the read_alf command and additional libraries are merged using the read_library_update command.

To enable communication between BuildGates synthesis and the DPCM, the following Unix environment variables must be set: DCMRULEPATH, DCMTABLEPATH, and LD_LIBRARY_PATH for Solaris (or the equivalent for other platforms). Refer to load_dcl_rule in the Envisia and Ambit Synthesis Command Reference and/or the

Using IEEE 1481 Delay and Power Calculation System (DCL) Libraries section in the Envisia Timing Analysis User Guide.

Ambit BuildGates Synthesis User Guide

Flow Procedures

The OLA specification is an extension of the Delay and Power Calculation System and is loaded in the same manner as the DCL: with the load_dcl_rule command after read_alf. Some of the key extensions to OLA over DPCS are the addition of cell function information and properties equivalents to dont_use and dont_touch which can be used for synthesis.

The .lib format is the ASCII synthesis timing and power library format originally defined by

Synopsys™ and now licensed by Synopsys through the TAP-in™ program. Cadence is a

TAP-in licensee. The Cadence library compiler, libcompile, supports the .lib format and produces a binary .alf file. Run the libcompile command from the Unix prompt (not from ac_shell) to compile a .lib file as follows:

libcompile xy_cells.lib xy_cells.alf

For exact libcompile syntax, refer to the Envisia Timing Analysis User Guide.

Graybox modeling is a practical solution for incorporating standard functions in the form of commercially available cores. These reusable IP (Intellectual Property) cores are predesigned and pre-verified functional building blocks that enable a major productivity gain for ASIC and IC design. In addition, Graybox modeling is also used in design situations in which the chip designer does not want to pass the netlist to the synthesis tool due to IP reasons. For these IP blocks, no re-synthesis or optimization is performed but timing validity must be ensured. Graybox modeling is supported in the .lib format. Run the libcompile command with the -ipformat option from the Unix prompt to compile a .lib file with graybox modeling:

libcompile -ipformat xy_cells.lib xy_cells.alf

The following paragraphs list the GUI and command line steps to: read a library, update this library with additional information from the update file, and load the DCL rules.

Read Library — GUI Procedure

1.Select File – Open – Ambit Library.

2.Browse for or type-in the path and file name and click Ok.

3.On the ac_shell console type read_library_update libfile.alf and press

Return.

4.Select Commands – Load DCL Rules.

Ambit BuildGates Synthesis User Guide

Flow Procedures

Read Library — Command Line Procedure

Note, the Unix environment variables DCMRULEPATH, DCMTABLEPATH, and

LD_LIBRARY_PATH (see Read the Libraries on page 95) must be loaded prior to these steps.

1.Type read_alf libfile.alf and press Return.

2.Type read_library_update libfile.alf and press Return.

3.Type load_dcl_rule and press Return.