- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
Report Generation
Design Rule Violations Reports
The report for the design rule violations of the netlist can be generated using the following command:
report_design_rule_violations [-hierarchical] [-ignore_clknet] [-current_module_only] [-verbose] [-ignore_dont_modify_nets] [{ > | >> } filename]
where:
■filename specifies the name of the report file. If filename is not specified, the report is displayed on standard output. filename must be the last argument in the list.
The -current_module_only option reports only the violations in the current module.
The -hierarchical option reports the violations for hierarchical ports.
The -ignore_clknet option prevents the reporting of the clock net violations.
The -ignore_dont_modify_nets option does not report design rule violations for nets that are set dont_modify.
The -verbose option reports all design rules for every net and port in the design regardless of whether there were any violations.
September 2000 |
198 |
Product Version 4.0 |
Ambit BuildGates Synthesis User Guide
Report Generation
Sample Design Rule Violations Report
Below is a sample design rule violations report generated from the following command:
report_design_rule_violations -hierarchical > BG4.0_des_rule_vio_rep.rpt
+----------------------------------------- |
|
|
+ |
| Report |
| |
report _ design _ rule _ violations | |
|
|--------- |
+ |
------------------------------- |
| |
| Options | |
- hierarchical |
| |
|
+--------- |
+------------------------------- |
|
+ |
| Date |
| |
20000727.170054 |
| |
| Tool |
| |
ac _ shell |
| |
| Release | |
v4.0 - eng |
| |
|
| Version | |
Jul 26 2000 08:19:39 |
| |
|
+--------- |
+------------------------------- |
|
+ |
| Module |
| |
cpu |
| |
+----------------------------------------- |
|
|
+ |
**** Design Rule Violation Report ****
Module: decode [decode1]
Net: sel_dat |
|
|
|
Max Capacitance |
= |
0.60 |
(i_823:Z [NR2]) |
Net Capacitance |
= |
0.69 |
|
VIOLATION |
= |
-0.08 |
|
Module: alu [alu1] |
|
|
|
Net: n_145 |
|
|
|
Max Capacitance |
= |
0.29 |
(i_6:Z [NR4]) |
Net Capacitance |
= |
0.54 |
|
VIOLATION |
= |
-0.25 |
|
Module: cpu |
|
|
|
Net: n_648 |
|
|
|
Max Capacitance |
= |
0.60 |
(decode1:sel_dat [decode]) |
Net Capacitance |
= |
0.69 |
|
VIOLATION |
= |
-0.08 |
|
3 violation(s) found. |
|
|
|
September 2000 |
199 |
Product Version 4.0 |