- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
7
Optimizing Before Place and Route
This chapter describes the flow and the commands used to invoke and control various optimization stages before place and route to produce a desired netlist. Logic optimization plays a key role in the synthesis process and consists of several processes, including: boolean transformations, flattening, structuring, technology-independent and -dependent mapping, hierarchical optimization, and context derivation.
The examples in this chapter are presented in command line input format and may not include all possible options; the syntax is for example only. For complete descriptions of all commands and their options, please refer to the Envisia and Ambit Synthesis Command Reference.
The hierarchical block diagram shown in Figure 7-1 will be used throughout this chapter to illustrate the use of various optimization commands.
Figure 7-1 Hierarchy of an Example Block
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The purpose of this chapter is to familiarize you with the command used to optimize before place and route, consequently, only a subset of the optimize commands are provided in the way of example. Also, the optimize examples in this chapter are presented in command line input format; GUI instructions are not provided. In addition, the example syntax may not include all possible options; the syntax is for example only.
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The logic synthesis process can be thought of in two steps: technology-independent optimization followed by technology dependent mapping and optimization.
After HDL modules are read, the functions (operations) are mapped to Ambit Technology
Library (ATL) cells and eXtended Ambit Technology Library (XATL) cells using the do_build_generic command. Some of the complex operations (e.g. addition, subtraction, increment) are also mapped to cells in AWACL components. If you have a license for the datapath option, a different set of components are used during mapping (refer to Datapath Synthesis on page 14 for a description of the datapath option).
For all the modules read in, a technology-independent netlist mapped to cells in ATL and
XATL libraries is created. If a module description has not been read in but the instance of such modules exist in other module descriptions that make up the design, such instances are treated as black boxes until the corresponding modules have been read and linked with the rest of the design.
Running do_optimize Command
The simplest way to optimize your design is with the do_optimize command. The do_optimize command runs a series of do_xform_ commands that provide a basic and thorough optimization routine. Figure 7-2 provides a diagram referred to as the “onion,” which shows the ”layers” of do_xform_ commands run by do_optimize. Command names within the layers of the onion are transforms and have a prefix of do_xform_. For example,
“propagate_constants” in the do_xform_optimize_generic layer is actually do_xform_propagate_constants.
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Figure 7-2 Layers of the do_optimize “Onion”
do_optimize command |
do_xform_optimize_generic |
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propagate_constants |
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structure |
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remove_redundancy |
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map |
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restructure |
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resize |
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buffer |
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clone |
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reclaim_area |
fix_design_rule_violations
do_xform_timing_correction |
do_xform_optimize_slack |
Note: Command names within the layers of the onion are transforms and have a prefix of do_xform_.
As shown in Figure 7-2, the do_optimize command runs the following four transforms, which in turn (with the exception of do_xform_map) run additional transforms:
■do_xform_optimize_generic
■do_xform_map
■do_xform_optimize_slack
■do_xform_timing_correction
For detail on the transforms, refer to Optimizing with Logic Transforms on page 177.
The do_optimize command applies to the hierarchy in and under the current module, set by the set_current_module command (for further information on this command, see Setting a Hierarchical Context on page 135). The results of optimization are stored in the database and must be retrieved using report_ and write_ group of commands.
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The syntax of the do_optimize command is extensive and is defined in the Envisia and
Ambit Synthesis Command Reference.
Top-Down Optimization
Typically, designs that are not very large can be fully optimized in a single run. In this case, optimization is performed from the top level without first individually optimizing lower level modules. This process is referred to as top-down optimization.
The following commands are useful in top-down optimization:
■do_build_generic
■do_optimize
■set_dont_modify
■do_dissolve
■do_uniquely_instantiate
Details of these commands are provided in this chapter and in the Envisia and Ambit Synthesis Command Reference.
Bottom-Up Optimization
When a design is very large, it may take too long to synthesize the entire design in a single run. In this case, lower level modules can be optimized individually first with constraints derived from top level constraints. These optimized lower-level modules are then “stitched together” and marked dont_modify. Then the next level of hierarchy is optimized until all levels up to and including the top level are optimized. This process is referred to as bottomup optimization.
The following commands are useful in bottom-up optimization:
■do_build_generic
■do_derive_context or do_detime_budget
■do_uniquely_instantiate
■set_dont_modify
■do_optimize
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