Ambit BuildGates Synthesis User Guide

Setting Constraints

Technology and Design Rule Constraints

A technology library contains both functional and timing information. The functional information is represented using operators and equations. The timing information includes specification of propagation delays within each cell and wire delays. During the cell selection process in logic synthesis, these delays are used to ensure that all the timing requirements

(constraints) are met. However, for accurate timing analysis, other aspects must be accounted for their impact on delay calculations considered, e.g. variation in operating condition, wire loads, fanout, etc.

Operating Conditions

The technology library contains timing data about all the cells at nominal voltage, temperature and process. You must consider how the variations in these conditions affect factors such as resistance, capacitance, propagation delay, etc. In turn, these factors affect the cell selection during the synthesis process. Hence, it is important that the operating condition be specified for a particular synthesis run to approximate the real circumstances under which the design will be used.

Each technology library contains one or more operating conditions. The set_operating_conditions command is used for setting the operating conditions. Each operating condition is identified by name, specifying process, voltage, and temperature. This information is used in calculating accurate cell delays from the nominal cell delays and the k- factors (also called derating factors) using either a linear model or non-linear model.

The syntax for the command is as follows:

set_operating_conditions [-library library_name] operating_conditions_name [-pvt min | typ | max]

where:

■library_name is the name of the technology library

■operating_conditions_name is the name of the operating condition in the library.

If only one technology library is used, the library option is not required.

Estimating Capacitance and Resistance

The delay information in the technology library applies to the timing arcs from input ports to output ports of each cell and the wire delays. The cell delays and the wire delays are expressed as a function of the physical characteristics of the nets in the design such as wire

Ambit BuildGates Synthesis User Guide

Setting Constraints

capacitance and wire resistance. In order to perform meaningful analysis before physical design, these parameters must be estimated. These estimates are derived from the models called wire load models.

Two commands effect wire load model determination: set_wire_load and set_wire_load_mode.

The technology library contains information about different wire load models. A wire load model is a function that uses the fanout count of a net and estimates its capacitance and resistance. A technology library contains different wire load models that are pre-computed based on the analysis of several designs differing in area. Typically, the technology libraries have an area lookup table that gives the wire load model for a given cell area of a design. Additionally, the floor planning tools may determine a specific wire load model for a design based on an initial physical design. These wire load models can be read in using read_library_update command; refer to the Envisia and Ambit Synthesis Command Reference for details.

The wire load can be set on the current module using the set_wire_load command;. the syntax is as follows:

set_wire_load [-library library_name] [-pvt min | typ | max ] [-hier]

wireload_model list_of_instances

where:

■library_name is name of the technology library to search.

■wireload_model is the name of the wire load model in the library.

■list_of_instances are the instances associated with the model.

The set_wire_load command applies to the module that is set as the current module using set_current_module command, and the wire load estimation is applied to all nets in the current module using the lookup table. If wire load model is not specified (i.e. no lookup table), then the delays are estimated based on the a wire load model determined from the area of the current module. See Wire Load Model Selection on page 163 for the wire load model selection algorithm.

In the absence of a user-specified wire load model, the set_wire_load_mode command controls the determination of the wire model; the syntax is as follows:

set_wire_load_mode [top | enclosed]

If enclosed mode is specified, the wire load model is selected using an area lookup table for the module at the lowest level in design hierarchy that contains the entire wire (net). If top mode is specified, the wire load model is selected using the area lookup table of the top level

Ambit BuildGates Synthesis User Guide

Setting Constraints

module (as set by set_top_timing_module command). The default wire load selection mode is top.

Port Capacitance

The port capacitance refers to the capacitance external to the design as seen by the input or output port of the design. The capacitance at any port is defined as the sum of external port capacitances to which the the port is connected (see Figure 6-17). For example, for input port

(A), the port capacitance refers to the capacitance of all the ports of the drivers on the net that connect to the input ports (C1, C2) and the capacitance of other loads on the net (C3). For an output port (Q), the port capacitance refers to the capacitance of the all the input ports of the cells that the output port is driving (C5, C6) and the capacitance of the input port of any other external drivers on this net (C4).

Figure 6-17 Distributed Capacitance at Input and Output Ports

The set_port_capacitance command sets the capacitance on an input port or an output port; the syntax is as follows:

set_port_capacitance float port_list [-pvt min | typ | max]

where:

■float is the capacitance value

■port_list is the list of ports with this capacitance

Ambit BuildGates Synthesis User Guide

Setting Constraints

Capacitance Limit

The capacitance limit constraint is specified on top level input and output ports. The limit is the maximum value for the total capacitances (wire capacitance and pin capacitance) of nets attached to the ports in the port list. The set_port_capacitance_limit command overrides the default limit set by the set_global capacitance_limit command.

The syntax is as follows:

set_port_capacitance_limit float port_list

where:

■float is the capacitance limit.

■port_list is the list of ports with this capacitance limit.

Fanout

The input ports of each cell have fanout loads that are related to the number of transistors connected to the port in the cell. Similar to setting port capacitance, setting the fanout load of a port is done with the set_fanout_load command.

The syntax is as follows:

set_fanout_load load port_list

where:

■load is the total fanout load external to the design.

■port_list is the list of ports with this load.

While the port capacitance affects timing analysis, fanout loads are used to enforce the design rule checks.

Fanout Limit

The fanout limit specifies the fanout load limit (maximum value) on the ports of a cell and are used to enforce the design rule checks. The design rule requirement of a maximum fanout load value is set using the set_global attribute fanout_load_limit. For the specified ports, the set_fanout_load_limit command overrides the default fanout load limit defined by set_global fanout_load_limit.

The set_fanout_load_limit command syntax is as follows: