Ambit BuildGates Synthesis User Guide

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Introduction to Ambit BuildGates Synthesis

This chapter provides a description of the Ambit® BuildGates® synthesis software, including brief descriptions of the three software options that are offered. This chapter also provides a comparison table of dc_shell and ac_shell command equivalents.

Capable of running in both command line mode and in graphical user interface (GUI) mode, the BuildGates synthesis tool delivers dramatic performance and productivity benefits over conventional synthesis tools. The key features of the Ambit BuildGates synthesis tool are described in the following paragraphs.

At the heart of the Ambit BuildGates synthesis tool is a signoff-quality, fast, full-chip timing engine that enables high-capacity and high-performance chip-level synthesis. Fast and flexible, BuildGates synthesis supports a wide variety of design styles such as multiple clocks, including both edge triggered and level sensitive with cycle stealing.

BuildGates synthesis has a high capacity database that allows synthesis of more of the design at once. Its fast runtime assures rapid turnaround making chip-level synthesis practical. In addition, high capacity enables productivity gain by eliminating the need for excessive resources and time required for elaborate bottom-up script development.

BuildGates synthesis also offers automatic time budgeting, integration with physical design tools, VHDL and Verilog support, support of both reads and writes of netlist EDIF 2.0, Tcl command line interface for shell level control, transforms for performing focused optimizations, schematic and textual report capabilities, and integrated DFT analysis and scan insertion.

Separately Licensed Software Products

Envisia™ low power synthesis, Envisia physically knowledgeable synthesis (PKS), and

Envisia datapath synthesis are companion products to the basic Ambit BuildGates synthesis software and require separate licenses. For details on these products, please contact your

Ambit BuildGates Synthesis User Guide

Introduction to Ambit BuildGates Synthesis

Cadence marketing representative. If you are a licensed user, the appropriate software and documentation are included in your installation package.

Low Power Synthesis

The low power module provides both power analysis and power optimization capabilities.

Power analysis estimates the power consuming modules in your design at the gate-level through each phase of the design cycle until you have met your power specifications. The power optimizer synthesizes a minimum power netlist that meets your specified timing constraints, optimizing design power consumption at the register-transfer level (RTL).

Licensed users can refer to the Envisia Low Power Synthesis User Guide for details.

Physically Knowledgeable Synthesis

Envisia physically knowledgeable synthesis (PKS) performs placement-driven timing by adding a physical model of the netlist to the timing and interconnect models that currently exist in the Ambit BuildGates synthesis tool. The physical model allows for timing estimation to take place during the optimization process, virtually eliminating the need for third-party placement tools.

Placement information is read into PKS using a PDEF file, which includes the x,y location of every cell. PKS uses highly accurate Steiner routes to estimate interconnect, resulting in closer correlation between the timing in BuildGates synthesis and the timing that results after running a place and route tool.

Licensed users can refer to the Envisia Physically Knowledgeable Synthesis User Guide for details.

Datapath Synthesis

The Envisia datapath synthesis product performs complex arithmetic operations that manipulate data in the RTL (in Verilog or VHDL format) to aid in the development of sophisticated, high-performance ASICs. Arithmetic components such as adders, subtractors, multipliers, comparators, and shifters are used to define the mathematical properties of the design.

Licensed users can refer to the Envisia Datapath Synthesis User Guide for details.