- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
Optimizing with Logic Transforms
■do_xform_clone
■do_xform_fix_design_rule_violations
■do_xform_fix_hold
■do_xform_fix_multiport_net
■do_xform_footprint
■do_xform_map
■do_xform_optimize_slack
■do_xform_propagate_constant
■do_xform_reclaim_area
■do_xform_remove_redundancy
■do_xform_resize
■do_xform_restructure
■do_xform_structure
■do_xform_timing_correction
■do_xform_unmap
■do_xform_optimize_generic
The do_optimize command can be replaced by the following do_xform* commands:
■do_xform_optimize_generic
■do_xform_map - heir
■do_xform_optimize_slack
Logic Optimization Steps
You can perform logic optimization in several different ways using several different approaches. This section outlines one possible method that works well in practice. The process of logic optimization can be broken down into the following steps:
1.Optimizing generic logic
2.Mapping of generic logic to technology-specific logic cells
3.Constraint-driven optimizing of technology-specific logic cells
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A description of these steps and the transforms that implement them are included in the following sections.
Optimizing Generic Logic
These optimizations operate on generic technology-independent representations of the underlying logic of a design and minimize generic logic.
The do_dissolve command operates on both generic technology-independent and mapped logic. It is used for small designs or small blocks of unstructured logic which span module boundaries. A design which has been dissolved will be structured all at once during do_xform_structure and care should be taken to insure that the unstructured design is not prohibitively large. The do_xform_optimize_generic command dissolves softwaregenerated hierarchies that are smaller than a predetermined threshold.
Table 8-1 lists the transforms that operate on technology-independent representations of a design.
Table 8-1 Transforms—Technology-Independent Representations
Transform Description
do_xform_propagate_cons Evaluates the value at all input ports and then if it is a
tant |
constant propagates that value to all submodules in the |
|
hierarchy. This transforms simplifies operations |
|
(additions, comparisons, etc.) involving constants and |
|
reduces the area of the design. |
|
|
do_xform_remove_redunda |
Minimizes the logic by removing portions which are |
ncy |
redundant or can be expressed using less logic. The |
|
-hierarchical option directs it to perform this |
|
transformation throughout the design hierarchy starting |
|
at the current module. |
|
|
do_xform_structure |
Structures logic to exploit common sub-expressions and |
|
terms. The operation of this transform is controlled by |
|
the option -priority area|time. The structuring |
|
and grouping are different depending on the priority |
|
specified. It structures logic expressions so sub- |
|
expressions and terms can be shared or replicated to |
|
improve area and timing respectively. If you have spent |
|
a lot of effort structuring your logic in the RTL |
|
description of your design, you may wish to avoid this |
|
step of logic optimization for a particular module. It is |
|
optional, but needed for good results in most cases. |
|
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Table 8-1 Transforms—Technology-Independent Representations, continued
Transform Description
do_xform_optimize_gener Performs the following sequence of all-generic ic optimizations:
do_dissolve do_xform_propagate_constant do_xform_structure do_xform_remove_redundancy
Mapping and Unmapping of Generic Logic
A single transform performs the mapping step do_xform_map. Each time do_xform_map is called, portions of the logic are unmapped and then remapped according to the criteria specified. Although a single mapping may be sufficient, additional mappings can provide more precision. Table 8-2 defines three mapping passes to illustrate various uses of the transform.
Table 8-2 Mapping of Generic Logic
Mapping Pass |
Description |
|
|
do_xform_map -hier |
Performs a straighforward mapping using the |
|
minimum area possible. |
|
|
do_xform_map -hier -timing |
Adds the -timing option which directs the |
|
mapper to perform mappings on |
|
combinational blocks with cell selection |
|
based on timing. |
|
|
do_xform_map -hier -timing |
Directs the mapper to operate on regions of |
-critical_offset 0.1 |
logic within 0.1 ns of the critical patha |
-fanin_depth 3 -fanout_depth 3 |
including 3 levels of logic fanning in or out of |
|
the critical section/path. |
|
|
a.The region as defined by the 0.1 -critical_offset range (worst slack) is a dynamic quantity which changes as optimization proceeds. Therefore, the size of the interval during each pass of the transform is a function of the worst slack in the current implementation of the design.
The do_xform_unmap command will undo all of the previous mapping steps and unmaps to generic gates. Buffering and drive-strength changes to improve timing do not appear in the
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unmapped resulting logic; however, certain changes in the logic structure (such as cloning) may persist.
Constraint-Driven Optimizing
Table 8-3 lists the transforms that improve the logic speed of critical paths.
Table 8-3 Transforms—Improve the Logic Speed of Critical Paths
Transform |
Description |
|
|
do_xform_buffer |
Inserts buffers that fix design rule violations |
|
(excessive fanout, slew-time, etc) on a net or to |
|
improve timing. |
|
|
do_xform_clone |
Clones segments of logic which drive nets with a |
|
large number of fanouts. |
|
|
do_xform_optimize_slack |
Performs an iteration of all constraint-driven |
|
optimizations. It is equivalent to the constraint- |
|
driven optimizations done in the do_optimize |
|
command. |
|
|
do_xform_reclaim_area |
Removes buffers, downsizes cells, and removes |
|
cloned logic without impacting the negative slack in |
|
the design. |
|
|
do_xform_buffer_tree |
Inserts buffer trees on all nets. |
|
|
do_xform_fast_optimize |
Uses a fast algorithm to simultaneously resize cells |
|
and insert buffers to improve timing. |
|
|
do_xform_resize |
Resizes the drive strengths of the cells, either |
|
upsizing or downsizing cells with the same |
|
functionality. |
|
|
do_xform_restructure |
Performs selective re-factorization of logic to |
|
improve timing while ensuring that the negative |
|
slack is not impacted This transform operates on a |
|
mapped netlist and performs selective unmapping |
|
and restructuring on logic in timing-critical regions. |
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