
- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference

Ambit BuildGates Synthesis User Guide
Report Generation
Area Reports
The report for the area of the netlist can be generated using the following command:
report_area [-summary] [-hierarchical] [-cells][{ > | >> } filename]
where:
■filename is the name of the generated report file. If filename is given, the report is written to the file. If the filename is omitted, the report is displayed on the standard output.
If the hierarchical option is used, the report is created for all the hierarchical modules in the current module, otherwise only the current module area is reported.
If the summary option is used, the area report only contains the summary information for the current module. This is the default option. The summary report includes the following information:
■Current module
■Wire load model
■Cell area
■Net area
■Total area
If the cells option is used, area report is printed on every cell in the current module. The cell report includes the following information:
■Summary report for current block
■Summary report cumulative for the current design hierarchy
■Name and count of cells used
■Type of cells used
■Area for each cell
■Total cell area
■Net area
■Total area
September 2000 |
193 |
Product Version 4.0 |

Ambit BuildGates Synthesis User Guide
Report Generation
Sample Area Report
Below is a sample area report generated from the following command:
report_area -summary -hierarchical > BG4.0_area_rep.rpt
+------------------------------------------------------- |
|
|
|
|
+ |
|
| Report |
| report_area |
|
| |
|
||
|--------- |
|
+--------------------------------------------- |
|
|
| |
|
| Options |
| -summary -hierarchical > BG4.0_area_rep.rpt | |
|
||||
+--------- |
|
+--------------------------------------------- |
|
|
+ |
|
| Date |
|
| 20000621.103245 |
|
| |
|
|
| Tool |
|
| ac_shell |
|
| |
|
|
| Release |
| v4.0-eng |
|
| |
|
||
| Version |
| Jun 19 2000 06:11:48 |
| |
|
|||
+--------- |
|
+--------------------------------------------- |
|
|
+ |
|
| Module |
| reg8_1 |
|
| |
|
||
+------------------------------------------------------- |
|
|
|
|
+ |
|
Summary Area Report |
|
|
|
|||
------------------- |
|
|
|
|||
+---------------------------------------------------------------- |
|
|
|
|
|
+ |
| |
Module | |
Wireload | |
Cell Area | |
Net Area | Total Area | |
||
|------------ |
|
+------------ |
+ |
------------+ |
------------+------------ |
| |
| |
reg8_1 | |
B0.5X0.5 | |
84.00 | |
13.83 | |
97.83 | |
|
+---------------------------------------------------------------- |
|
|
|
|
|
+ |
September 2000 |
194 |
Product Version 4.0 |