- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
Setting Constraints
set_fanout_load_limit load_limit port_list
where:
■load_limit is the fanout load limit on the specified ports.
■port_list is the list of ports with this fanout load limit.
External Sources and Sinks
The external sources and sinks at a port specify the number of sources and sinks to the net which is connected to the ports that are external to the design. If you set the number of external sources or sinks on a port, then the port capacitance for such a port should include only the external port capacitances. The total wire capacitance of a net is automatically computed using the asserted external sources and sinks and results in an accurate delay computation. The set_num_external_ commands may be omitted if the port capacitance includes internal wire capacitances.
The syntax for the commands is as follows:
set_num_external_sources num port_list
set_num_external_sinks num port_list
where:
■num is the non-negative integer number of sources or sinks.
■port_list is the list of ports with the specified number of sources or sinks.
The source and sink numbers are factored into the wire capacitance and the wire resistance estimation done for the port nets using the wire load models. The value does not add towards the total fanout count for Design Rule Violation (DRV).
Wire Capacitance
After the physical design is complete, you can back-annotate capacitance on each net and re-analyze the netlist for timing (see Figure 6-18). The syntax for setting the wire capacitance command is as follows:
set_wire_capacitance float net_names [-pvt {min, typ, max}]
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Ambit BuildGates Synthesis User Guide
Setting Constraints
where:
■float is the wire capacitance.
■net_names is a list of nets with this capacitance.
Figure 6-18 Wire Capacitance
Source |
Sink |
source res |
sink res |
source cap net cap |
sink cap |
Wire Resistance
Similar to the capacitance specification, you can also specify resistance for each net after the physical design is done. The syntax for setting the wire resistance command is as follows:
set_wire_resistance float net_names [-pvt {min, typ, max}]
where:
■float is resistance value.
■net_names is a list of nets with this resistance.
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