- •Contents
- •Preface
- •About This Manual
- •Other Information Sources
- •Syntax Conventions
- •Text Command Syntax
- •About the Graphical User Interface
- •Using Menus
- •Using Forms
- •Introduction to Ambit BuildGates Synthesis
- •Separately Licensed Software Products
- •Low Power Synthesis
- •Physically Knowledgeable Synthesis
- •Datapath Synthesis
- •AC_Shell / DC_Shell Equivalencies
- •Getting Started
- •Invoking Ambit BuildGates Synthesis
- •Exiting Ambit BuildGates Synthesis
- •Files Used in Ambit BuildGates Synthesis Software
- •Key Bindings and Mouse Operations
- •Using the GUI
- •Main Menu Functions
- •File Menu Options
- •Edit Menu Options
- •View Menu Options
- •Commands Menu Options
- •Reports Menu Options
- •Window Menu Options
- •Help Menu Options
- •The Tool Bar
- •The Browsers
- •The Module Browser
- •The Variable Browser
- •Work Area Tools
- •HDL and Tcl Editors
- •Constraints Tool
- •The Schematic Viewer
- •Distributed Processing
- •Update Mode
- •The ac_shell Console
- •The Status Bar
- •Flow Procedures
- •Typical Synthesis Flow
- •Read the Libraries
- •Read the Design Data
- •Build Generic Netlist
- •Set Constraints
- •Optimize the Design
- •Generate Reports
- •Save Final Netlist
- •Viewing the Schematic Design
- •How to Use the Schematic Viewer
- •Keyboard Shortcuts
- •Mouse Operations
- •Objects in the Schematic Database
- •Accessing Context-Sensitive Pop-Up Menus
- •Highlighting Path Between Pins
- •Viewing Bus Properties
- •The Schematic Tool Bar
- •The Module Title Bar
- •Searching for an Object
- •Grouping Instances
- •Dissolving Instances
- •Creating a Unique Module
- •Displaying Logic Cones
- •Extracting Logic Cones
- •Displaying Port Constraints
- •Printing a Schematic
- •Setting Constraints
- •Setting a Hierarchical Context
- •Units in Constraints
- •Timing Constraints
- •Timing Analysis
- •Setting up Timing Context
- •Clock Insertion Delay Time
- •Data Arrival Time
- •External Delay
- •Multicycle Paths
- •Setting Drive Cell for Input Ports
- •Setting Drive Resistance
- •Slew Related Commands
- •Technology and Design Rule Constraints
- •Operating Conditions
- •Estimating Capacitance and Resistance
- •Port Capacitance
- •Capacitance Limit
- •Fanout
- •Fanout Limit
- •External Sources and Sinks
- •Wire Capacitance
- •Wire Resistance
- •Wire Load Model Selection
- •Optimizing Before Place and Route
- •Running do_optimize Command
- •Top-Down Optimization
- •Bottom-Up Optimization
- •Deriving Constraints from Context
- •Time Budgeting
- •Preserving Module Contents
- •Uniquifying Instances
- •Collapsing Hierarchy
- •Incremental Optimization
- •Applying Timing Corrections
- •Optimizing with Logic Transforms
- •Introduction to Transforms
- •Logic Optimization Steps
- •Optimizing Generic Logic
- •Mapping and Unmapping of Generic Logic
- •Constraint-Driven Optimizing
- •Summary Listing of Transform Commands
- •Optimizing After Place and Route
- •Timing Analysis
- •Backannotating
- •A Script Showing the Backannotation of a Design
- •Reading SDF Data
- •Optimizing to Correct Late and Early Slack
- •Report Generation
- •Report Header
- •Timing Reports
- •Area Reports
- •Sample Area Report
- •Library Reports
- •Hierarchy Reports
- •Sample Hierarchy Report
- •Design Rule Violations Reports
- •Sample Design Rule Violations Report
- •VHDL Library Reports
- •Sample VHDL Library Report
- •End Point Slack and Path Histogram Reports
- •Fanin and Fanout Reports
- •Sample Fanin Report
- •Finite State Machine Reports
- •Sample FSM Report
- •Customizing Report Column Width
- •Using Tcl within ac_shell and pks_shell
- •The Tcl Language
- •Procedures
- •Tcl Variables and Control Structures
- •Variables
- •Syntax
- •Tcl Commands
- •get_names Command
- •Abbreviating Commands
- •Searching for Commands
- •Accessing Environment Variables
- •Returning Unix Command Values
- •Error Handling
- •Quick Reference
Ambit BuildGates Synthesis User Guide
Setting Constraints
(including setup time) before the arrival of the clock. In other words, the required time for data signal at the output port of your design is calculated by subtracting the propagation delay through the logic from the clock arrival time at the register of the downstream block.
For example, the following command sets external delay of 4.1 on the output port pout which is driving the input to a register that is controlled by the leading edge of the ideal clock clk.
set_external_delay -lead -clock clk 4.1 pout
Note that if set_data_required_time command and set_external_delay command are used on the same output port, only set_data_required_time is accepted. If set_data_required_time command is not used, but multiple set_external_delay commands are used, then the worst case required time is established for timing analysis.
Multicycle Paths
By default, all paths in a design are considered single cycle paths. However, certain paths in the design are multicycle paths, i.e. the signal propagation from the start point to the end point spans over multiple cycles. The timing information for multicycle paths can be specified using set_cycle_addition command. The sample syntax is as follows:
set_cycle_addition [{-from|-from_rise|-from_fall} [{-through|-through_rise|-through_fall} [{-to|-to_rise|-to_fall} pinlist][-clock_from [-edge_from {leading | trailing}] [-clock_to
[-edge_to {leading | trailing}] [-rise | -fall] [-early | -late]
[-target] float
where:
■pinlist are the pins involved in the multicycle paths.
■list_of_clocks are the ideal clocks involved in the multicycle paths.
■target is the clock used to calculate cycle adjustment.
■float is the N-1 number of extra cycles added to the path (can be negative to reduce the number of cycles in the path).
The from option indicates the pin name at the start of the multicycle path. All paths originating from the from pin get extra cycles as specified by the float. This can be viewed as decreasing the arrival time delay at the from by the specified by float.
The to option indicates the pin name at the end of the multicycle path. All paths ending at the specified pin(s) get extra cycles as specified by float.
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If from option is used without the to option, all paths originating from the from pin will be considered as multicycle paths with the float. For example, the command:
set_cycle_addition -from I1/Q 2
indicates that all paths from port Q of instance I1 should be considered as 3 cycle paths (2 additional cycles) as shown in Figure 6-8. Each path may end at different cell instances in the design. There is only one float value stored at I1/Q.
Figure 6-8 Multiple Paths Starting from Pin I1/Q
I1 |
2 |
path1 |
Q 2
path2
2
path3
If the to option is used without the from option, all paths ending in pinlist are considered as multicycle paths with the float value. The float is stored unconditionally at the pins in pinlist for all paths terminating at the list. For example:
set_cycle_addition -to I2/A 1
The above command indicates that all paths ending in port A of instance I2 should be treated as 2 cycle paths (1 additional cycle) as shown in Figure 6-9. Each path may have originated from different pins and different module instances. There is only one float value stored at I2/
A.
Figure 6-9 Multiple Paths Ending at Pin I2/A
path1 |
1 |
I2 |
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path2 |
1 |
A |
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path3 |
1 |
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|
|
If both from and to options are used, all paths between the pins are considered as multicycle paths with the float value. The float at the to pin is stored conditionally for each path originating at the specified from pin. The float for the paths terminating at the to pin that were specified without the from pin (see to option above) remain stored at the to pin unconditionally. For example:
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Setting Constraints
set_cycle_addition -from I1/Q -to I2/A 2
The above command indicates that both path1 and path2 between port Q of instance I1 and port A of instance I2 are 2 cycle paths (see Figure 6-10), thus decreasing the signal arrival time at port A by 2 cycles.
Figure 6-10 Multiple Paths between Pins I1/Q and I2/A
I1 |
path2 |
I2 |
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||
Q |
path1 |
A |
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|
Note that if one set_cycle_addition command is used with only to option, and another set_cycle_addition command is used with both to and from options at the same to pin (irrespective of the order in which they are executed), the path between the from pin and the to pin has two different float values. For this particular path, the float value specified in the command with from and to options will override the float value at stored at the to pin specified in the command with only to option. When a path is defined either with only to option, or with both from and to options, the float is stored at the to pin; the from pin is not affected.
During the timing analysis phase, the float stored at from pins and to pins are added to the signal arrival times.
In the example shown in Figure 6-11, all paths from port A of instance I1 are two cycle paths (p3, p4, p5), all paths ending in port B of instance I2 are also 2 cycle paths (p1, p2, p3), and all paths between the ports A and B are single cycle paths (p3).
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Setting Constraints
Figure 6-11 Describing Multicycle Paths
I3 |
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p1 |
I2 |
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C |
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p2 |
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B |
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p3 |
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I1 |
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p4 |
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A |
I4 |
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p5 |
D |
These multicycle paths are described with the following set_cycle_addition commands:
set_cycle_addition -from |
I1/A |
1 |
// affects p3, p4, p5 |
set_cycle_addition -to I2/B 1 |
|
// affects p1, p2, p3 |
|
set_cycle_addition -from |
I1/A |
-to I2/B -1 // overrides p3 at I2/B |
|
The first command indicates that all paths starting at port I1/A are 2 cycle paths (p3, p4, p5), decreasing the arrival time at port I1/A for all paths by 1 cycle. The float for these three paths is stored unconditionally at the port I1/A. Table 6-1 describes the float stored at each port after the first command is executed. There is no float stored at the port I1/A for paths p1 and p2. The float at the port I2/B is not affected.
Table 6-1 Float Value Stored at From Pin (After First Command)
|
Path |
Pin |
|
|
|
|
I1/A |
I2/B |
|
|
|
p1 |
x |
x |
p2 |
x |
x |
p3 |
1 |
x |
p4 |
1 |
x |
p5 |
1 |
x |
x indicates no change (initialized to 0)
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Setting Constraints
The second set_cycle_addition command in the example above indicates that all paths ending in port I2/B are 2 cycle paths (p1, p2, p3), decreasing the arrival time at port I2B for all paths by 1 cycle. The float value for these three paths is stored unconditionally at the port I2/B, causing I1/A-->I2/B path (p3) to have decreased the arrival times twice.
Table 6-2 describes the float value stored at each port after the second command is executed.
Table 6-2 Float Value Stored at To Pin (After Second Command)
|
Path |
Pin |
|
|
|
|
I1/A |
I2/B |
|
|
|
p1 |
x |
1 |
p2 |
x |
1 |
p3 |
1 |
1 |
p4 |
1 |
x |
p5 |
1 |
x |
x indicates no change due to this command
The third set_cycle_addition command in the example above overrides the unconditional float value specified at the to pin for all the specific paths ending at the to pin. The paths not identified by the third command are not affected. The float value at the port I2/B will now be replaced with -1 as specified in the third command. The value -1 was set as the cycle time in order to specify a single cycle path from I1/A-->I2/B (p3), i.e. the sum of the two cycle values (at I1/A and I2/B) should be zero. Table 6-3 describes the float value stored at each port and the net effect on the path after the third command is executed.
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