Ambit BuildGates Synthesis User Guide

Setting Constraints

Figure 6-4 Associating a Negative Clock Signal to an Ideal Clock

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Data Arrival Time

Signal changes arrive at input ports of a design at certain times. In general, the arrival of a signal change at an input port of a block is controlled by the output port of another block which is eventually driven by a register or primary input to the design. Therefore, the arrival time of a signal for an input port (also called a data port) is associated with the clock edge that causes the signal change, as shown schematically in Figure 6-5.

Figure 6-5 Associating Input Delay at Input Port with Ideal Clock

Logic

clock

ck

Previous Block

Current Module

The command set_input_delay is used to specify the signal input delay at input port(s); the sample syntax is as follows:

set_input_delay [-lead|-trail] [-rise|-fall] [late|-early] [-clock clock_name] time pinlist

where:

■clock is the name of the ideal clock associated with the register causing change.

■time is the input delay, an integer or real constant.

Ambit BuildGates Synthesis User Guide

Setting Constraints

■pinlist is the list of pins for which the arrival time is specified.

The lead/trail options refer to the pertinent edge of the ideal clock with which the signal arrival time is specified. If omitted, it defaults to lead.

The rise/fall options indicate whether the arrival time refers to a rising edge at the input port or the falling edge. If omitted, the data arrival time applies to both the edges at the input port.

For example,

set_input_delay -clock master -lead -fall 6.4 D

Here, the falling edge transition of the data signal arrives at input port D at 6.4 ns after the leading edge of the clock master. It is associated with the leading transition of the ideal clock master. Since the rising edge transition is not specified, it is not considered in the timing analysis.

The clock specification is not necessary when the signal arriving at the output port is generated through purely combinational logic.

The early/late options refer to the changing of the signal at the input port. The early option indicates the earliest time the signal can arrive (change) at the input port. This implies that the signal at the input port will remain stable with its value in the previous clock cycle at least as long as the specified time. The late option indicates the latest time the signal can arrive (change) at the input port. This implies that the signal at the input port will not have a change after the specified time. If this option is omitted, the default is both early and late time.

The signal at the input port may change between the early and late times. When an input port is driven from multiple paths, it is common to have a fast path and a slow path that cause the change in the signal at the input port. The early and late options allow you to specify the earliest time at which the fast path can change the signal and the latest time that the slow path can change the signal. Refer to Figure 6-6.

Ambit BuildGates Synthesis User Guide

Setting Constraints

Figure 6-6 Early and Late Arrivals of a Signal

The example in Figure 6-6 shows two paths for input port D. The signal at D can change (rising or falling) as early as 5.3 ns due to change on path labeled path1 and a falling edge as late as 6.4 ns due to change on path labeled path2. In this example, both paths are associated with the leading edge of the ideal clock master. The resulting commands for these paths are as follows:

set_input_delay -clock master -lead -early 5.3 D set_input_delay -clock master -lead -late -fall 6.4 D

The arrival time at all input ports can be specified using the find command instead of listing individual ports. As shown below, the find command evaluates to a list of all the input ports of a given block.

set_input_delay -clock master 1.6 [find -port -input *]

If an input port is already identified as a clock port using the set_clock_root command, then the set_input_delay command for that port is ignored. Conversely, if set_input_delay command was applied to set arrival time on an input port and later the same port was used to set clock signal delay using set_clock_root command, the clock delay is ignored on the input port.

Ambit BuildGates Synthesis User Guide

Setting Constraints

External Delay

An alternate way to specify the data required time at the output port is to consider the timing requirement of the configuration of the downstream block to which the output port is connected. If you know the critical path from the output port of your block to the register of the downstream block, then you can describe the configuration and the required time using set_external_delay command. See Figure 6-7.

Figure 6-7 Specifying External Delay at an Output Port

The sample syntax is as follows:

set_external_delay [-rise|-fall] [-late|-early] [-lead|-trail] [sig | ref][-clock clock] [-arrival float] external_delay portlist

where:

■clock is the name of the ideal clock controlling the external register.

■float is the actual arrival time of the edge of the clock being used to determine external delay.

■external_delay is the external delay, including setup. (integer or real constant).

■portlist is the list of ports.

The lead or trail options refer to the pertinent edge of the ideal clock controlling the external register. If omitted, it defaults to lead.

The rise or fall options indicate whether the external delay refers to a rising edge at the output port or the falling edge. If omitted, the external delay applies to both edges at the output port.

The required time at the output port is computed as if the output port is driving a register external to the design. The data signal must arrive at the input of the external register